Tektronix, Inc.

Ronald M Jackson

Russell Y Anderson

Daniel C Olin

A logic analyzer stores the activity around the last in a series of triggering events while also storing the activity around several other triggering events immediately preceding the last trigger. The acquisition memory is first positioned into a number, N, of memory sections and the trigger condition of interest is defined. Then repeated acquistions are performed using this same trigger condition. At first, data from each of these acquisitions is stored in each one of the number of memory sections. When all of the memory sections have been filled once, if the trigger condition is still occurring, the acquisition memories are reused in the same order in which they were originally used as many times as necessary until it is ascertained that the trigger condition is no longer occurring or some external conditon has changed, at which time the logic analyzer is stopped. One of the memory sections then contains the data that occurred in the vicinity of the last trigger. Another of the memory sections contains data reflecting the activity that immediately preceded the stopping of the logic analyzer. The remaining N-2 memory sections contain data that occurred in the vicinity of the triggers that immediately preceded the last trigger. Timestamping the acquired data allows the timing relationships involved to be reconstructed.

Method for acquiring data in a logic analyzer

A method for performing signal quality analysis on digital signals uses simultaneous dual threshold data acquisition. Using this method, the data need not be repetitive and, because the reference data and the variable data are acquired simultaneously, the logic analyzer continues to trigger and further measurements can be made after significant noise has been encountered. One threshold is designated the reference threshold and used to perform triggering and acquisition of reference data, while the other threshold is designated the variable threshold and used to acquire data for the noise margin analysis. At each increment of variable level, the data acquired by the reference acquisition and the data acquired using the variable threshold level is compared to see at what point in time and on what signal lines noise begins to affect the quality of the data. These data comparisons should be tolerant of minor timing variations that arise from the interaction of normal rise and fall times and the varying threshold level, and yet be sensitive to more significant changes in the data that arise from the effects of noise, marginal signal width or amplitude, or excessive rise and fall times.

Digital signal quality analysis using simultaneous dual-threshold data

A logic analyzer has a counter/timer that can reconstruct the higher resolution with which data was acquired using multiple phases of the logic analyzer system clock signal. For a two-phase data sampling system, separate pairs of event recognizers monitor the data collected using the two phases of the system clock. Counter/timer control logic uses the information from these separate pairs of event recognizers to control the behavior of the counter/timer so that it can either single count or double count, depending on whether an event was true during both phases or only one phase of the data acquisition, thus allowing the counter/timer resolution to be as high as the information inherent in the data acquired using both clock phases. The counter/timer employed is capable of single or double counting and has two stages, a prescaler and an extension counter/timer, for increased power and cost effectiveness. An event recognizer is capable of recognizing words, ranges, unstable data, glitches, and/or other signal characteristics.

Enhanced counter/timer resolution in a logic analyzer

A circuit allows digital data acquisition instruments to recognize when dual threshold synchronous data being monitored in unstable. Each data line being monitored for unstable periods is compared with a high threshold level and a low threshold level at an acquisition probe and the results of these two comparisons are forwarded to the circuit of the present invention. Optionally, a glitch latch may be employed to cause transient crossings of the threshold to be treated as if they lasted until the next clock. The two bits of resulting information are each clocked through a short shift register consisting of two flip-flops. A gate monitoring each of these short shift registers produces an active output when the state of the two flip-flops indicates that the signal left the high state or left the low state. A third gate monitors the last flip-flop in each short register to produce an active output when the signal is neither high nor low. The outputs of these three gates are summarized by a fourth gate to provide a local unstable signal for that single data line. The results across all of the lines being monitored are ORed into an unstable signal indicating the status of all of the lines being monitored. Individual enable signals determine which lines are to be monitored for instability at any one time. A counter/timer may be used to monitor the unstable signal for setup and hold time violations with respect to a clock signal.

Unstable data recognition circuit for dual threshold synchronous data

A data transfer synchronization method and circuit allows data to be transferred between two synchronous systems running asynchronously with each other in a way that does not require the receiving system clock to be running twice as fast as the source system clock. Data is clocked into a first set of flip-flops by the clock signal of the source system. The source system clock signal is also used to toggle a toggle flip-flop. The receiving system clock signal is used to clock a first clock bit flip-flop coupled to detect the state of the toggle flip-flop. A delayed version of the receiving system clock signal is used to clock the output of the first set of flip-flops into a second set of flip-flops. The normal (undelayed) receiving system clock signal is used to clock the output of the second set of flip-flops into a third set of flip-flops. A data valid signal is generated when the third set of flip-flops have on their outputs the data received during receiving system clock cycles in which the toggle flip-flop toggled. If the toggle flip-flop did not toggle during a particular receiving system clock cycle, no data valid signal is produced because this data is either redundant or uncertain due to insufficient guaranteed setup time.

Digital data transfer synchronization circuit and method

Disclosed herein is an apparatus for displaying a logic waveform on a raster scan display device such as a CRT. A part of an input logic signal is delayed for forming a former bit, and the input logic signal acts as a present bit. A memory device stores a special pattern determined in accordance with results of logic operation of the present and former bits. An image dot of the pattern is addressed by the present and former bits and raster line position (number) information, and the output therefrom is applied as an intensity control signal to the display device. Since the memory device does not need FONT information, this invention needs very little software manipulation of data, and the capacity of the memory device is small. In addition, this invention can display glitches and graticule tick marks.

Logic waveform display apparatus

Apparatus for displaying a logic timing diagram on a raster scan type display device is disclosed. A logic signal is sampled and representations thereof stored in a RAM. The RAM contents are read repeatedly in synchronism with a raster scan operation, and the read-out signal is delayed by a predetermined time which is shorter than one bit cycle of the read-out signal. Logical gating functions, OR, exclusive-OR and NAND gates, receive the delayed and undelayed signals, and provide output signals from which the display of the 'High' level, edges and 'Low' level of the logic timing diagram are derived. Since it is not necessary to convert the logic signal to display codes and rewrite a display RAM, high speed scrolling and magnification can be obtained quickly and easily.

Logic timing diagram display apparatus

A programmable delay circuit comprises input and output multiplexers, a delay device provided between the multiplexers, and a negative feedback path. When the input multiplexer selects an input logic signal, the delay time is controlled by the output multiplexer. When the input multiplexer selects the feedback path, the delay circuit acts as a ring oscillator for generating a square-wave signal whose period is twice the selected delay time. Additional delay devices and multiplexers may be provided between the input and output multiplexers.

Growing community of inventors

Portland, OR, United States of America

Ronald M Jackson