Hughes Aircraft Company

Hughes Electronics Corporation

He Holdings, Inc.

Ronald M Finnila

Stephen C Su

Ronald L Williams

Donald C Mead

Dale G Maeding

Joseph J Bendik

Gerard T Malloy

A self adjusting tiled image display system and method is provided. In operation, an image source having an array of tiled image displays projects a test image pattern. A positioning device is attached to a corresponding one of the image displays for positioning that image display. A sensor senses the test image pattern projected by the image displays and generates a sensor signal indicative of the sensed test image pattern. A processor compares the sensor signal to a proper alignment signal indicative of the image displays being properly aligned to generate a positioning signal. The processor applies the positioning signal to the positioning devices to position the image displays as a function of the positioning signal until the image displays are in the proper alignment.

Self adjusting tiled projector using test pattern and sensor

A method of operating a liquid crystal display, and a liquid crystal display constructed to operate in accordance with the method. The liquid crystal display has a plurality of display pixels, and the method comprises the steps of (a) operating a first switch (S1) for storing a charge on a storage capacitance (C1), the charge having a magnitude selected so as to cause a desired degree of polarization of a region (pixel) of liquid crystal material; (b) operating a second switch (S2) so as to conductively couple the stored charge to the region of liquid crystal material, thereby storing a charge on a capacitance (C2) that is associated with the region of liquid crystal material; and (c) operating a third switch (S3) so as to discharge the storage capacitance and the capacitance that is associated with the region of liquid crystal material. Also disclosed is a method of fabricating a display assembly that comprises a layer of liquid crystal material and a plurality of drive circuits that are formed within a common layer of semiconductor material.

Point addressable display assembly, method of operating same, and method

A microelectronic device is fabricated by furnishing a first substrate (40) having a silicon etchable layer (42), a silicon dioxide etch-stop layer (44) overlying the silicon layer (42), and a single-crystal silicon wafer (46) overlying the etch-stop layer (44), the wafer (46) having a front surface (52) not contacting the etch stop layer (44). A microelectronic circuit element (50) is formed in the single-crystal silicon wafer (46). The method further includes attaching the front surface (52) of the single-crystal silicon wafer (46) to a second substrate (58), and etching away the silicon layer (42) of the first substrate (40) down to the etch-stop layer (44). The second substrate (58) may also have a microelectronic circuit element (58') therein that can be electrically interconnected to the microelectronic circuit element (50).

Process of manufacturing a microelectric device using a removable

A method of providing a first and a second Silicon-on-Insulator (SOI) wafer, wherein each SOI wafer includes a silicon layer separated from a bulk silicon substrate by a layer of dielectric material, typically SiO2. Next, at least one electrical feedthrough is formed in each of the silicon layers and active and passive devices are formed in each of the thin silicon layers. Next, interconnects are formed that overlie the silicon layer and are electrically coupled to the feedthrough. One of the wafers is then attached to a temporary substrate such that the interconnects are interposed between the thin silicon layer and the temporary substrate. The bulk silicon substrate of the wafer having the temporary substrate is then etched to expose the dielectric layer. Further interconnects are then formed through the exposed dielectric layer for electrically contacting the at least one feedthrough. This results in the formation of a first circuit assembly. A next step then couples the further interconnects of the circuit assembly to the interconnects of the second SOI wafer, the second SOI wafer having a bulk substrate, a dielectric layer overlying a surface of the substrate, and a layer of processed silicon overlying the dielectric layer. The temporary substrate is then removed. Additional circuit assemblies may then be stacked and interconnected to form a 3d integrated circuit.

Process of manufacturing a three dimensional integrated circuit from

A method and apparatus for improving the operation of infrared detectors of a type generally characterized by a semiconductive substrate of a first conductivity type which includes a detection region defined or bounded by a heavily doped backside electrode and buried layer of the first conductivity type. A charge coupled device (CCD) readout structure for transfers charge in an epitaxial layer of second conductivity type which overlies the substrate, and the detector further includes a heavily doped layer of the second conductivity type positioned between the epitaxial layer and the substrate to shield the charge carriers of the substrate from the CCD voltages. Means are provided by the present invention for the injection of minority charge carriers into the epitaxial region which are subsequently transferred to output means by the CCD. The substrate is biased so that a portion of the flow of minority carriers in the epitaxial layer will be diverted toward the backside electrode when the detection region is raised to conduction by the incidence of photon energy so that a subtractive indication of the radiation is obtained while harmful double injection and attendant substrate breakdown are avoided.

Signal detection method for IR detector having charge readout structure

There is disclosed an all silicon monolithic focal plane array of infrared detectors for image detection. The structure comprises two epitaxial layers grown on an extrinsically doped silicon substrate. The detectors are formed in and extend through the substrate, the material of which is sensitive to specific wavelength infrared signals according to the dopant used in the substrate. The collection of charges takes place on a first buried layer formed around a portion of the first epitaxial layer-substrate interface, and the charges are then transferred through a second buried layer of the same conductivity type to a conducting surface layer on the upper portion of the second epitaxial layer. The signal readout function is performed by a charge coupled device shift register constructed in the second epitaxial layer by providing selectively spaced electrodes in an insulating layer. Carriers generated in the detector by incident infrared radiation are collected into the first buried layer and then pass through the second buried layer to the surface layer and they are injected therefrom into the CCD shift register and are detected at the output. The monolithic construction and the use of an epitaxial layer to form the CCD shift register result in high yield and high efficiency devices. The use of two epitaxial layers in the device improves its responsivity, its fill factor and better isolates the operation of its CCD circuits from its detector elements.

Monolithic extrinsic silicon infrared detector structure employing

There is disclosed an all silicon monolithic focal plane array of infrared detectors for image detection. The structure comprises an epitaxial layer grown from an extrinsicly doped silicon substrate. The detectors are formed in and extend through the substrate the material of which is sensitive to specific wavelength infrared signals according to the dopant used in the substrate. The signal readout function is performed by a charge coupled device shift register constructed in the epitaxial layer by separating electrodes from it in an insulating layer formed on it. Carriers generated in the detecor by incident infrared radiation are directly injected into the CCD shift register and detected at the output end. The monolithic construction and the use of an epitaxial layer to form the CCD shift register results in low cost, high yield and high efficiency devices.

Monolithic extrinsic silicon infrared detectors with charge coupled

There is disclosed an all silicon monolithic focal plane array of infrared detectors for image detection. The structure comprises an epitaxial layer grown on an extrinsically doped silicon substrate. The detectors are formed in and extend through the substrate, the material of which is sensitive to specific wavelength infrared signals according to the dopant used in the substrate. The collection of charges takes place on a buried layer formed around a portion of the epitaxial layer-substrate interface, and the charges are then transferred through a surface layer of the same conductivity type to the surface of the epitaxial layer. The signal readout function is performed by a charge coupled device shift register constructed in the epitaxial layer by providing selectively spaced electrodes in an insulating layer. Carriers generated in the detector by incident infrared radiation are collected into the buried layer and then pass through the surface layer, are injected therefrom into the CCD shift register and are detected at the output. The monolithic construction and the use of an epitaxial layer to form the CCD shift register result in high yield and high efficiency devices. The planar surface of the device improves the aluminum step coverage for a more reliable device, and the use of the buried layer improves the fill factor of the detector.

Monolithic extrinsic silicon infrared detectors with an improved charge

A device for performing Haddamard transform operations including a first matrix of interconnected electronic cells, and a second matrix of interconnected electronic cells connected to the output of the first matrix, the electronic cells being charge coupled devices. A rectangular wave generator is electronically connected to the first and second matrices. The first matrix comprises a plural number of rows of such electronic cells serially connected to each other, the output of each one of the rows being connected to an input of each one of the cells corresponding to one of the rows of the second matrix. As a result a solution of on-focal plane Haddamard transform is obtained by recording the Haddamard sequencies at a common terminal of the second or output matrix.

Haddamard electronic readout means

There is disclosed a circuit for removing the DC or background representing charge component of a signal to be passed through a charge coupled device shift register without degrading the information carried by the AC component of the signal. Such a circuit may, for example, be used to remove the constant background illumination component of the input from a semiconductor imaging device to increase the contrast ratio of the image signal. The circuit comprises two electrode defined potential wells or buckets formed in a semiconductor substrate with a control gate between them and a transfer gate which controls the flow of the charges in the first bucket to a P-N junction. Like the well defining electrodes, the control gate and transfer gate are electrodes separated from the semiconductor substrate by an insulation layer. The transfer gate functions as a channel switch to control the flow of the background charges from the first bucket through the P-N junction to an external drain in discrete quantized increments under the control of an appropriate clock voltage on the transfer electrode. This subtraction of the DC component from the signal passing through the shift register results in a reduction in the size of the storage electrodes required to transmit a given quantity of signal charge through the shift register for fixed clock voltages and thereby makes more economical use of the chip area.

Growing community of inventors

Carlsbad, CA, United States of America

Ronald M Finnila