Micrel, Incorporated

Advanced Micro Devices Corporation

Ronald Lloyd Schlupp

John Durbin Husher

Jayasimha Prasad

Jay Albert Shideler

Robert William Bechdolt

Mammen Thomas

William L Price

Linda Koyama

A power lateral PNP device is disclosed which includes an epitaxial layer; a first and second collector region embedded in the epitaxial layer; an emitter region between the first and second collector regions. Therefore slots are placed in each of the regions. Accordingly, in a first approach the standard process flow will be followed until reaching the point where contact openings and metal are to be processed. In this approach slots are etched that are preferably 5 to 6 um deep and 5 to 6 um wide. These slots are then oxidized and will be subsequently metalized. When used for making metal contacts to the buried layer or for ground the oxide is removed from the bottom of the slots by an anisotropic etch. Subsequently when these slots receive metal they will provide contacts to the buried layer where this is desired and to the substrate when a ground is desired. In a second approach the above-identified process is completed up through the slot process without processing the lateral PNPs. With a separate masking and etching the oxide is removed from the PNP slots and boron is deposited in a diffusion furnace and driven in a non oxidizing atmosphere.

Method and system for providing a power lateral PNP transistor using a buried power buss

Embodiments of a bipolar transistor are disclosed, along with methods for making the transistor. An exemplary transistor includes a collector region in a semiconductor substrate, a base layer overlying the collector region and bound by a field oxide layer, a dielectric isolation layer overlying the base layer, and an emitter structure overlying the dielectric isolation layer and contacting the base layer through a central aperture in the dielectric layer. The transistor may be a heterojunction bipolar transistor with the base layer formed of a selectively grown silicon germanium alloy. A dielectric spacer may be formed adjacent the emitter structure and over a portion of the base layer.

Method of fabricating a bipolar transistor using selective epitaxially grown SiGe base layer

A method for improved dielectric polish control adjacent to device areas is described. This is particularly important for bipolar structures, although the method may be used for MOS structures as well. The method includes using highly selective methods for removing oxide layers and polish stop layers in a multi-layer film stack, providing an oxide edge step height that is substantially uniform regardless of the size of the adjacent device area. In one embodiment, the multi-film stack includes a first oxide layer, first nitride layer, second oxide layer, and second nitride layer. The multi-film stack is deposited on a substrate. Trenches are then etched through the multi-film stack and into corresponding regions of the substrate. A passivation oxidation layer is grown on the etched trench surfaces. The trenches are filled with oxide for isolating active device regions from one another. A first STI polish is performed, polishing the trench oxide to the level of the second nitride layer, which is then removed. The second oxide layer is then removed. A second STI polish is then performed, polishing the trench oxide to the level of the first nitride layer, which may then be removed. The oxide step height at the edge of each active device region is then approximately equal, regardless of the size of the device region, with a height approximately equal to the thickness of the first nitride layer.

Multi-layer film stack polish stop

An improved process is disclosed for making an integrated circuit structure wherein a trench is etched into one or more layers to electrically separate one of the devices in the integrated circuit structure from other portions thereof by first patterning silicon dioxide and silicon nitride layer on a layer of silicon. The improvement comprises isotropically etching the silicon layer to provide an enlarged shallow etch area undercutting the patterned silicon dioxide and silicon nitride layers. Subsequent deeper anisotropic etching to form the trench will result in a trench having an enlarged upper width which, in turn, prevents the formation of voids adjacent the upper portion of the trench during subsequent oxidation and polysilicon deposition steps. Possible creation of openings to such voids in the polysilicon during subsequent planarization is thereby eliminated thus avoiding undesirable oxidation of such voids and undesirable stress formation therefrom.

Process for formation of trench in integrated circuit structure using

A merged platinum silicide fuse and Schottky diode structure and method of manufacturing the merged structure is presented. The merged structure is formed by an insulating layer having an aperture over a silicon substrate. A shaped layer of polysilicon lies on the insulating layer and contacts the substrate through the aperture; a layer of platinum silicide in the same shape as the polysilicon layer covers the polysilicon layer. The region of polysilicon - PtSi layers over the substrate contact forms a Schottky diode and the region on the insulating layer forms the fuse. This merged structure has superior Schottky diode electrical characteristics and is more compact compared to prior art structures.

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Los Gatos, CA, United States of America

Ronald Lloyd Schlupp