International Business Machines Corporation

Ronald Lee Mendelson

Donald W Brouillette

Eric Gerhard Liniger

Robert F Cook

Thomas George Ference

Wayne John Howell

Michael Straight Hibbs

Harold G Linde

William Thomas Motsiff

John M Blondin

David Frederick Diefenderfer

Stephen Peter Ayotte

Timothy M Sullivan

Sylvain E Ouimet

Jeffrey D Gilbert

David J Hill

Jean-Guy Quintal

Richard Charles Whiteside

Dean R Sanders

Methods for making, and structures so made for producing integrated circuit (IC) chip packages without forming micro solder balls. In one embodiment, a method may include placing a solid grid made from an organic material between the IC chip and the substrate. The grid provides a physical barrier between each of a plurality of Controlled Collapse Chip Connections, and thereby prevents the formation of micro solder balls between them, thus improving chip performance and reliability.

Production of integrated circuit chip packages prohibiting formation of micro solder balls

A method and apparatus for controlling the thickness of a semiconductor wafer during a backside grinding process are disclosed. The present invention uses optical measurement of the wafer thickness during a backside grinding process to determine the endpoint of the grinding process. Preferred methods entail measuring light transmitted through or reflected by a semiconductor wafer as a function of angle of incidence or of wavelength. This information is then used, through the use of curve fitting techniques or formulas, to determine the thickness of the semiconductor wafer. Furthermore, the present invention may be used to determine if wedging of the semiconductor occurs and, if wedging does occur, to provide leveling information to the thinning apparatus such that a grinding surface can be adjusted to reduce or eliminate wedging.

Wafer thickness control during backside grind

A method and system for dicing a semiconductor wafer providing a structure with greatly reduced backside chipping and cracking, as well as increased die strength. Semiconductor chip structures obtained from wafers diced according to this invention are also encompassed.

Method and system for dicing wafers, and semiconductor structures incorporating the products thereof

A structure (and method) for a metallurgical structure includes a passivation layer, a via through the passivation layer extending to a metal line within the metallurgical structure, a barrier layer lining the via, a metal plug in the via above the barrier layer, the metal plug and the metal line comprising a same material, and a solder bump formed on the metal plug.

Copper pad structure

A method for forming a wirebond connection to an integrated circuit structure includes forming an insulative structure overlaying a corrosion susceptible metal wiring within the integrated circuit structure, defining a via through the insulative structure above a portion of the corrosion susceptible metal without exposing the portion of the corrosion susceptible metal, and attaching a wirebond material to the portion of the corrosion susceptible metal. The attaching process includes a preliminary process of exposing the portion of the corrosion susceptible metal. The attaching completely covers the portion of the corrosion susceptible metal.

Wirebond passivation pad connection using heated capillary

A semiconductor structure with greatly reduced backside chipping and cracking, as well as increased die strength, accommodation of compact assembly with a carrier such as another semiconductor chip, and resistance to package damage is provided by dicing chips from a wafer in a manner that chamfers edges of the chips. Similar advantages are obtained in multi-chip structure.

Semiconductor structure and package including a chip having chamfered edges

A method for sorting integrated circuit chips. At least one physical defect is detected in the semiconductor chips. The semiconductor chips are sorted based upon the physical defect.

Mechanical strength die sorting

A method is described by which the mechanical strength of chips of semiconductor devices can be controlled by appropriate wafer finishing and sorted by knowledge of the finishing method and chip and wafer geometry. The control and sorting derive from a knowledge of the geometry of the striations remaining on the back of chips after the wafer-grinding finishing step.

Method and apparatus for preventing chip breakage during semiconductor manufacturing using wafer grinding striation information

A method for manufacturing a low profile semiconductor chip, includes fabricating a semiconductor device on a semiconductor wafer, grinding, with a grinding tool, a backside of the semiconductor wafer to reduce a thickness thereof, and with the wafer in the grinding tool, providing a support structure on the ground backside of the wafer.

Method for mounting wafer frame at back side grinding (BSG) tool

A serpentine pattern has been found to be effective at interrupting propagation of delamination cracks in thin film layers. The ring is provided on a semiconductor chip to suppress crack propagation from the chip edge. The ring is effective even though it is filled with metal, the serpentine pattern providing significantly increased area as compared with a standard linear crack stop that the energy for crack propagation is dissipated. In addition to serpentines, pattern features such as staggered filled ring patterns and connected rings will also be effective at reducing the propagation of delamination cracks from edge to active area by virtue of the increased area of interaction between the crack and the crack stop.

Growing community of inventors

Richmond, VT, United States of America

Ronald Lee Mendelson