Agere Systems Inc.

Lucent Technologies Inc.

At&t Bell Laboratories

Bell Telephone Laboratories

American Telephone & Telegraph Co., At&t Bell Laboratories

Ronald Lamar Freyman

Lane Allen Smith

Vladimir Sindalovsky

Craig B Ziemer

Mohammad Shafiul Mobin

Malcolm Harold Smith

Bruce W McNeill

Clinton Hays Holder, Jr

Gary H Weiss

Yehuda Rotblum

Isik C Kizilyalli

Ross Alan Kohler

Omkaram Nalamasu

Richard Muscavage

Joseph Rudolph Radosevich

Max Jay Olsen

Paul David Hendricks

George Patrick Watson

Mark Richard Pinto

Steven P Pekarich

Edward Clayton Morgan

Charles Raymond Miller

Michael James Hunter

Ted R Martin

Craig Joseph Garen

Robert M Vella

Robert Nelson Kershaw

Evelyn M Fields

A voltage controlled delay loop and method are disclosed for clock and data recovery applications. The voltage controlled delay loop generates clock signals having similar frequency and different phases. The voltage controlled delay loop comprises a plurality of delay elements; and an input that selectively injects a reference clock into any one of the plurality of delay elements. The plurality of delay elements are connected in series, such as in a loop. In one exemplary implementation, each delay element has an associated multiplexer that selects one of the reference clock and a signal from a previous delay element.

Voltage controlled delay loop and method with injection point control

Methods and apparatus are provided for improving phase switching and linearity in an analog phase interpolator. A phase interpolator in accordance with the present invention comprises (i) a plurality of tail current sources that are activated for substantially all times when the phase interpolator is operational; (ii) at least two pairs of input transistor devices, wherein one pair of the input transistor devices is associated with a minimum phase of the phase interpolator and another pair of the input transistor devices is associated with a maximum phase of the phase interpolator; and (iii) a plurality of current steering switches that provide currents generated by the plurality of tail current sources to one or more of the at least two pairs of input transistor devices, based on an applied interpolation control signal.

Methods and apparatus for improved phase switching and linearity in an analog phase interpolator

A method and apparatus are disclosed for generating phase controlled data, based on a roaming tap interpolator. The present invention recognizes that roaming tap interpolators have inherent nonlinearities and discontinuities at the boundaries of each interpolation region. A roaming tap interpolator is disclosed that shifts the interpolation curve in time in order to avoid the undesired artifacts in the interpolation curve. A roaming tap interpolator generally comprises a plurality of delay elements that delays a first signal to generate a plurality of interpolation regions each having an associated phase; a multiplexer to select one or more of the interpolation regions; and an interpolator to process the selected one or more of the interpolation regions to generate a second signal. In addition, according to the present invention, the roaming tap interpolator includes a delay unit that selectively delays one or more of the first signal and the second signal to generate an interpolation signal, the interpolation signal selectively having a first phase or a second phase.

Phase interpolator having a phase jump

The various embodiments of the invention provide an apparatus, system and method of asynchronous testing a serializer and deserializer data communication apparatus (SERDES) for determining frequency and phase locking to pseudo asynchronous input data having a continual phase offset. An exemplary apparatus includes a data sampler adapted to sample input serial data and to provide output data; a controlled tap delay with a selected tap having a phase offset from the input serial data, in which the selected tap is selectively coupleable to the data sampler to provide pseudo asynchronous input serial data; a first variable delay control adapted to delay a reference frequency provided to the controlled tap delay in response to the pseudo asynchronous input serial data; and a second delay control adapted to adjust the plurality of taps in response to the pseudo asynchronous input serial data. In additional embodiments, the pseudo asynchronous input serial data is provided from an interpolated phase from at least two selected taps.

Pseudo asynchronous serializer deserializer (SERDES) testing

A parallel trimming method and apparatus are provided for a voltage controlled delay loop. A plurality of delay units in a voltage controlled delay loop are trimmed. Each delay unit comprises a delay element and a latch buffer. A reference signal is applied to each of the delay units and a position of an edge (such as a rising or falling edge) associated with each of the delay units is identified. The edges of the delay units are then aligned by adjusting a trim setting of the respective latch buffer.

Parallel trimming method and apparatus for a voltage controlled delay loop

Methods and apparatus are provided for maintaining a desired slope of clock edges in a phase interpolator using an adjustable bias. The disclosed phase interpolator comprises at least one delay element to generate at least two interpolation signals each having an associated phase and a variable slope unit associated with each of the at least two interpolation signals, wherein a slope of each of the variable slope units is controlled by a bias signal and is varied based on a data rate of the interpolation signals. The slope is varied to maintain a desired slope of clock edges associated with the interpolation signals. The slope can be maintained, for example, between approximately the value of the delay between consecutive clock edges and twice the value of the delay between consecutive clock edges.

Methods and apparatus for maintaining desired slope of clock edges in a phase interpolator using an adjustable bias

A voltage controlled delay loop and method are disclosed for clock and data recovery applications. The voltage controlled delay loop generates clock signals having similar frequency and different phases. The voltage controlled delay loop comprises at least one delay element to generate at least two phases of a reference clock; a central interpolator for interpolating the at least two phases of the reference clock to generate an interpolated signal; and an input that injects the interpolated signal into a delay stage. The central interpolator provides a fine phase control. In addition, a coarse phase control can optionally be achieved by selectively injecting the interpolated signal into a given delay stage. A further voltage controlled delay loop is disclosed with coarse and fine phase control using a number of interpolators.

Voltage controlled delay loop with central interpolator

Methods and apparatus are provided for trimming a desired delay element in a voltage controlled delay loop. The disclosed trimming process comprises the steps of obtaining a first phase signal of a reference clock; applying the first phase signal along a first path to the desired delay element and a common delay element connected in series to the desired delay element; applying the reference clock along a second path to a first delay element and the common delay element; measuring a delay difference between the first and second paths at an output of the common delay element; and adjusting a delay of the desired delay element based on the measured delay difference. The trimming method may be repeated for each delay element in a voltage controlled delay loop.

Trimming method and apparatus for voltage controlled delay loop with central interpolator

A digit signal processor capable of operating at 100 MHZ with a 1.0 volt power supply. The digital signal processor is fabricated by application of strong phase-shift lithography to obtain a 0.12 &mgr;m gate dimension. A dual-mask process is utilized to improve resolution thereby producing high speed, low-voltage processors. A n /p dual-Poly:Si module, and dopant penetration suppression techniques may be utilized.

High speed low voltage semiconductor devices and method of fabrication

An integrated circuit includes topological features for weakening or otherwise modifying a blowable fuse in order to decrease the current needed to blow the fuse. This allows a decrease in the size of the circuit components which are needed to supply the current for blowing the fuse, in turn allowing compaction of the layout of the circuitry needed to blow the fuse. To this end, topological features are used to deform the shape of or otherwise modify the fuse, in turn increasing the resistance of the fuse or introducing flaws that allow the fuse to blow at a lower current.

Using topological features to lower the blowing current needed for fuses

Blowable fuses on an integrated circuit are programmed in software, responsive to the control of an addressable memory which communicates with the peripheral data bus of a digital processor to allow increased flexibility of the programming operation, and to allow for correction both during the manufacturing process and after packaging of the manufactured integrated circuit. In a preferred embodiment, the fuses are operated (i.e., blown) responsive to transistor switching elements present on the integrated circuit and which are controlled by the addressable memory. The switching elements, and the associated fuses, can be accessed through software in similar fashion to any other peripheral device. The preferred addressable memory includes an instruction register and a data register, which are loaded from and write to the peripheral data bus. Internally, the data register includes an array of registers corresponding to the fuse links with which the system is associated. Data words in the registers are written from or read to the data register tinder the control of instructions in the instruction register, and the fuses are then blown serially, by reference to the data in the registers.

Software programmable write-once fuse memory

An integrated circuit includes a power-up detector circuit that includes a node that is held at a charged state by a capacitor during normal operation. The voltage on the node is sensed by a sensing circuit, typically an inverter that produces a power-up reset pulse when power is initially applied. However, the voltage on the node may not properly discharge in all cases during brief power interruptions. Therefore, to increase the reliability of the power-up detector, a discharge circuit is included to help ensure that the voltage sensed by the power supply voltage-sensing circuit is at the proper level when the power supply voltage drops below a given level. The discharge circuit comprises a first capacitor that turns on a node discharge transistor when the power supply voltage drops below the given level. To provide protection against false discharge, a second capacitor is optionally provided that prevents the discharge transistor from conducting during very brief power supply voltage interruptions. In a preferred embodiment, the second capacitor is effectively disabled at low power supply voltages. This facilitates conduction of the discharge transistor for power supply voltage interruptions resulting from slow changes (low slew rate) in the power supply voltage.

Power-up detector circuit

There is disclosed an integrated circuit includes an output driver circuit providing control of transition time from one state to another. The output driver includes first and second input transistors coupled to an input node at which data is received. First and second output transistors are coupled to an output node at which the data is presented when the output driver is enabled. The first input transistor is coupled to the first output transistor defining a first node. The second input transistor is coupled to the second output transistor defining a second node. First and second switching circuits are coupled between the first node and the second node. The first switching circuit is switchable between a first state that isolates the first node from the second node, and a second state that couples the first node to the second node. The first switching circuit exhibits a characteristic upon being switched from one of the first or second states to the other, such as from the first state to the second state, that impacts turn-on time of one of the first and second output transistors. The second switching circuit is switchable between a first state that isolates the first node from the second node, and a second state that couples the first node to the second node. The second switching circuit also exhibits a characteristic that upon being switched from one of the first and second states impacts turn-on time of the other of the first and second output transistors.

Growing community of inventors

Bethlehem, PA, United States of America

Ronald Lamar Freyman