Advanced Micro Devices Corporation

North American Philips Corp, Signetics Division

Ronald L Treadway

Bertrand Jeffery Williams

Gregory K Goodhue

William J Price

Brian M Willis

A PLL architecture is disclosed which incorporates a coarse adjustment feedback loop and a fine adjustment feedback loop together providing a combined error signal to a single VCO. The coarse adjustment feedback loop includes two digital counters set to divide the VCO output frequency by two different numbers. The outputs of the counters are coupled to the inputs of respective phase-frequency detectors, and the pump-up output of one of the detectors and the pump-down output of the other detector are used as the coarse adjustment pump-up and pump-down signals, respectively, in the coarse adjustment feedback loop. The coarse adjustment feedback loop thereby establishes a frequency range limitation for the fine adjustment feedback loop.

Clock recovery phase lock loop having digitally range limited operating

Page-mode-organized ROMs and associated circuitry are connected only to data and control buses in an information processing system. Addressing and reading of the ROMs are controlled by a processor without connecting the ROMs to an address bus. Selection of a particular ROM and of a particular page in the selected ROM is accomplished by applying a first control signal to the control bus and a first data word to the data bus. This first data word thus serves as the address of the selected page in the selected ROM. Then a particular byte of the selected page is selected by applying a second control signal to the control bus and a second data word to the data bus. This second data word serves as the address of the selected byte. Subsequently, in response to a third control signal, the selected byte is read out of the selected ROM and applied to the data bus.

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Saratoga, CA, United States of America

Ronald L Treadway