Micron Technology Incorporated

Other

Round Rock Research, LLC

Ronald L Taylor

Brent Keeth

Larren Gene Weber

Layne G Bunker

John Stuart Mullin, Sr

Larry Duane Kinsman

Frank F Ross

Raymond J Beffa

Scott J Demer

A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. Sense amplifiers are positioned between adjacent rows in the individual arrays while row decoders are positioned between adjacent columns in the individual arrays. In certain of the gap cells, multiplexers are provided to transfer signals from I/O lines to datalines. A data path is provided which, in addition to the foregoing, includes array I/O blocks, responsive to the datalines from each quadrant to output data to a data read mux, data buffers, and data driver pads. The write data path includes a data in buffer and data write muxes for providing data to the array I/O blocks. A power bus is provided which minimizes routing of externally supplied voltages, completely rings each of the array blocks, and provides gridded power distribution within each of the array blocks. A plurality of voltage supplies provide the voltages needed in the array and in the peripheral circuits. The power supplies are organized to match their power output to the power demand and to maintain a desired ratio of power production capability and decoupling capacitance. A powerup sequence circuit is provided to control the powerup of the chip. Redundant rows and columns are provided as is the circuitry necessary to logically replace defective rows and columns with operational rows and columns. Circuitry is also provided on chip to support various types of test modes.

256 Meg dynamic random access memory

A tableware item having a body, and a magnifier on the body. A method for using such a tableware item to read printed material such as, but not limited to, a menu or wine list.

Tableware magnifier

A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. In certain of the gap cells, multiplexors are provided to transfer signals from I/O lines to data lines. A datapath is provided which, in addition to the foregoing, includes array I/O blocks, responsive to the datalines from each quadrant to output data to a data read mux, data buffers, and data driver pads. The write data path includes a data in buffer and data writes muxes for providing data to the array I/O blocks. Redundant rows and columns are provided as is the circuitry necessary to logically replace defective rows and columns with operational rows and columns. Circuitry is also provided on chip to support various types of test modes.

256 meg dynamic random access memory having a programmable multiplexor

A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. Sense amplifiers are positioned between adjacent rows in the individual arrays while row decoders are positioned between adjacent columns in the individual arrays. In certain of the gap cells, multiplexers are provided to transfer signals from I/O lines to data lines. A datapath is provided which, in addition to the foregoing, includes array I/O blocks, responsive to the datalines from each quadrant to output data to a data read mux, data buffers, and data driver pads. The write data path includes a data in buffer and data write muxes for providing data to the array I/O blocks. A power bus is provided which minimizes routing of externally supplied voltages, completely rings each of the array blocks, and provides gridded power distribution within each of the array blocks. A plurality of voltage supplies provide the voltages needed in the array and in the peripheral circuits. The power supplies are organized to match their power output to the power demand and to maintain a desired ratio of power production capability and decoupling capacitance. A powerup sequence circuit is provided to control the powerup of the chip. Redundant rows and columns are provided as is the circuitry necessary to logically replace defective rows and columns with operational rows and columns. Circuitry is also provided on chip to support various types of test modes.

A method and system for changing the connected behavior of a circuit design schematic at the time a netlist is being created by assigning instance parameters to each switch instance, the parameter having a value representing that the position of the switch is open or closed, the parameter being evaluated at the time the netlist is created to determine the position of the switch. When the netlist being created is a flat netlist, a closed switch condition is represented by printing information to the netlist file that identifies the nets being interconnected. When the netlist being created is a hierarchical netlist, the nets being interconnected are declared as 'artificial' ports, allowing these nets to be tracked through the hierarchy to instances at which the parameters are evaluated and to provide a connection between these nets, allowing the interconnection of nets to be specified at a level in the hierarchy other than that at which the switch is declared.

System and method for changing the connected behavior of a circuit

A method and device for scoping nets from a schematic in a hierarchical netlist. The device is a complementary subsystem to a hierarchical netlister software package. The device allows instances or subcircuits in a schematic to systematically reassign (i.e., scope) local nets which represent global nets to other local nets so that the use of such nets does not affect usage of the global nets elsewhere in the circuit. The device tracks all global nets and maps the corresponding scoped nets to their net identifiers. Then, as the netlister creates the hierarchical netlist, the device replaces the global net's net identifier with the correct net identifier of the corresponding scoped net.

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Meridian, ID, United States of America

Ronald L Taylor