Intel Corporation

Ronald L Dammann

James A McConnell

Steven R King

Narayanan G Kaniyur

Sujoy Sen

Frank L Berry

Robert Chan

David C Nadell

Satishkumar P Sampath

Percy K Wadia

Techniques are described herein that may utilize capabilities of a data mover in order to determine an integrity validation value or perform an integrity checking operation. The integrity validation value determination and integrity checking operations may be controlled by descriptors or instructions. In some implementations, integrity validation value determination and the integrity checking operations may include determination of a cyclical redundancy checking (CRC) value.

Techniques to determine integrity of information

In one embodiment, an interconnect device (e.g., a switch) includes an interface operably coupled to an interconnect logic capable of reducing inter-packet gaps in packet -based input/output communications. Based on, at least in part, a packet attribute associated with an inbound packet, the interconnect logic may determine an indication of transfer grant which may be issued in conjunction with a packet relay request, sending packet attribute information in advance of the packet attribute.

Reducing inter-packet gaps in packet-based input/output communications

A method, system, computer program product, and expansion card capable of: defining an initial source address within a source memory device. An initial data read operation is performed to retrieve a first X-byte data portion from the source memory device. The initial data read operation begins at the initial source address. The initial source address is incremented by Y bytes to define a secondary source address within the source memory device, such that Y is greater than X.

Integrated circuit capable of marker stripping

An interconnect device (e.g., a switch) includes a port operably coupled to a packet broadcaster for routing unicast and/or multicast packets of data in packet-based input/output communications. For an inbound packet, at least two combinations of a source port and one or more destination ports, and one or more destination paths associated with each of said one or more destination ports may be determined by the packet broadcaster in a single lookup of a memory (e.g., a random access memory).

Routing packets in packet-based input/output communications

In one embodiment, a method is provided. In the method of this embodiment, one operating mode of port circuitry may be selected from a plurality of operating modes of the port circuitry that may correspond to respective sets of one or more communication links via which the port circuitry may be capable of communicating when the port circuitry is operating in the respective operating modes. Each of the respective sets of one or more communication links may be different from each other. The method of this embodiment also may include selecting, based at least in part upon the one operating mode of the port circuitry, a set of filters. The port circuitry may be capable of determining, based at least in part upon the set of filters, whether to drop a packet that is received, or intended to be transmitted by the port circuitry.

Mechanism to support multiple port configurations

The present invention is directed to buffer arrangements (e.g., via concatenation) to support differential link distances at full bandwidth.

Buffer arrangements to support differential link distances at full bandwidth

A port configuration mechanism is provided at a host for multiple port allocation and shared resource utilization to support multiple port configurations for different port operation modes on a host to handle data transfers in a switched fabric data network for scalable solutions.

Growing community of inventors

Palo Alto, CA, United States of America

Ronald L Dammann