Xilinx, Inc.

Lattice Semiconductor Corporation

Philips Electronics North America Corporation

Koninklijke Philips Corporation N.v.

Ronald L Cline

Shi-dong Zhou

Andy T Nguyen

Stewart G Logie

Tim Tuan

Matthew H Klein

Gubo Huang

Arifur Rahman

Brad Sharpe-Geisler

Wayne Edward Wennekamp

Daniel Y Chung

James B Anderson

Ting Yew

Senani Gunaratna

Alan M Frost

Andy DeBaets

Bernardo De Oliveira Kastrup Pereira

Chin Hua Tan

Shankar Lakka

Ping Zhang

David Y Chung

Andrew J Debaets

One aspect relates to a memory circuit that has a programmable non-volatile memory (NVM) cell configured to generate an NVM output signal indicative of a program state of the NVM cell and to configure a volatile output based on the program state of the NVM cell. The NVM cell comprises a first anti-fuse device, a first select device connected in series with the first anti-fuse device at a first node, and a first pass device. The memory circuit also may have a programmable (independently of the NVM cell) volatile memory (VM) cell configured to receive the NVM output signal at a VM input node and to generate a VM output signal indicative of the program state of the VM cell. The NVM cell may have two NV elements that are separately programmable and are separately selectable via separate access transistors to drive the VM input node.

Memory circuit having non-volatile memory cell and methods of using

One aspect relates to a memory circuit that has a programmable non-volatile memory (NVM) cell configured to generate an NVM output signal indicative of a program state of the NVM cell and to configure a volatile output based on the program state of the NVM cell. The NVM cell comprises a first magnetic tunnel junction (MTJ) device, a first select device connected in series with the first MTJ device at a first node, and a first pass device. The memory circuit also may have a programmable (independently of the NVM cell) volatile memory (VM) cell configured to receive the NVM output signal at a VM input node and to generate a VM output signal indicative of the program state of the VM cell.

Various techniques are provided to efficiently implement selective power gating of routing resource configuration memory bits for programmable logic devices (PLDs). In one example, a PLD includes a routing circuit configured to selectively route input nodes to an output node. The PLD further includes configuration memory cells configured to store configuration bit values to control the routing circuit. The PLD further includes a power circuit configured to power the configuration memory cells while storing the configuration bit values. The PLD further includes an enable bit memory cell configured to store an enable bit value to interrupt at least one connection of the power circuit to the configuration memory cells. The configuration memory cells are configured to provide, in response to an interruption of the connection, default configuration bit values to the routing circuit to prevent routing the input nodes to the output node. Additional systems and related methods are provided.

Selective power gating of routing resource configuration memory bits for programmable logic devices

A method and circuit for device specific configuration of an operating voltage is provided. A circuit design is analyzed to determine a maximum gate-level delay for the circuit design. A minimum voltage value corresponding to the maximum gate-level delay is determined along with a default voltage value corresponding to a default gate-level delay. A voltage scaling factor corresponding to the minimum voltage and default voltage values is determined. The circuit design is synthesized such that the synthesized design includes the voltage scaling value. The synthesized design specifies setting an operating voltage to a value of a startup voltage value scaled by the voltage scaling value.

Device specific configuration of operating voltage

A method for determining a critical junction temperature for a user-design implemented in a field programmable gate array (programmable device), includes: obtaining a static power vs. temperature curve for the user-design implemented in the programmable device; obtaining a system thermal curve for the user-design implemented in the programmable device; and using the static power vs. temperature curve for the user-design implemented in the programmable device and the system thermal curve for the user-design implemented in the programmable device to determine the critical junction temperature.

Method for determining critical junction temperature

A method and circuit for operating a bistable latch are provided. The state of input data is latched on a first edge of a clock signal. In response to every first edge of the clock signal, a control circuit causes power boost circuit to couple first and second complementary output nodes of the bistable latch to a power source. In response to detecting stable operation of the bistable circuit, the control circuit causes power boost circuit to decouple the first and second complementary output nodes from the power source.

Bistable circuit with metastability resistance

A programmable integrated circuit having a plurality of individually controlled voltage domains. Each voltage domain includes logic circuitry powered by a respective power network. The voltage magnitude of each power network is independently selectable. Each of a plurality of level shifters couples a first and second one of the voltage domains, couples a first port of the logic circuitry of the first voltage domain to a second port of the logic circuitry of the second voltage domain, and shifts from a first signaling protocol of the first port to a second signaling protocol of the second port. The first signaling protocol is referenced to the voltage magnitude of the first voltage domain, and the second signaling protocol is referenced to the voltage magnitude of the second voltage domain. Means are disclosed for controlling the voltage magnitude of the respective power network of one or more of the voltage domains.

Programmable integrated circuit with voltage domains

An integrated circuit, such as a field programmable gate array or other configurable logic device, has an interconnect circuit selectively configurable to operate in a high-speed mode or in a low-power mode. The interconnect circuit is operable from a higher voltage supply or a lower voltage supply to change operating modes without reconfiguring data paths.

Integrated circuit with a selectable interconnect circuit for low power or high performance operation

A programmable differential signaling system includes a programmable bias generator and a plurality of input/output modules. The programmable bias generator is operably coupled to generate a first global bias signal and a second global signal based on desired signal properties of one of a plurality of differential signaling conventions. The a plurality of input/output modules is operably coupled to convert between differential signaling and single ended signaling, wherein actual signal properties of the differential signaling are regulated based on the first and second global bias signals to substantially equal the desired signal properties.

Programmable differential signaling system

A selectively enabled clamp circuit for limiting voltage overshoot on an input/output (I/O) pin of an associated integrated circuit (IC) device includes a single discharge transistor and a select circuit. The single discharge transistor is connected between the I/O pin and ground potential, and the select circuit is coupled to the I/O pin and includes an input to receive an enable signal and an output coupled to a gate of the signal discharge transistor. For some embodiments, the select circuit includes a level shifter circuit and a voltage detection circuit.

Overvoltage clamp circuit

Level shifter circuits that provide fast operation when changing state while generating little crowbar current. Various embodiments are presented that include some of the following features added to conventional level shifters: additional pull-down transistors coupled to each output node and gated by the associated input signal; additional pull-up transistors coupled to each output node or cross-coupled internal node and gated by the associated input signal; additional pull-up transistors coupled to the cross-coupled internal nodes and gated by the opposing output node; and additional pull-down transistors on the output nodes gated by a low voltage power high. Some of these additional transistors allow the input signal to operate more quickly on the output nodes, causing more rapid transitions on the output signals and reducing crowbar current. The pull-downs gated by the low voltage power high ensure that little or no crowbar current occurs during the power-up sequence.

High-speed, low current level shifter circuits for integrated circuits having multiple power supplies

A very fine-grained gate array cell is provided that includes a two-input logic device and a cascade NAND gate with buffered output. The NAND gate accepts a cascade input from another cell, and the cascade output of the NAND gate is provided as a cascade input to the other cell to facilitate the efficient implementation of cross-coupled devices. Each cell contains integral routing paths that facilitate a &ldquo;sea of cells&rdquo; layout approach. To ease the routing task, the output of each gate array cell is pre-wired so as to facilitate a programmed interconnection to each logic input of adjacent cells, near-adjacent cells, and far cells, and the aforementioned cascade interconnection with adjacent upper and lower cells. This configuration allows adjacent and near-adjacent cells to be easily interconnected to form macro cells that conform to higher level functional blocks. The gate array does not contain explicit routing channels; routing is effected using the prewired routing that is integral with each gate array cell.

Growing community of inventors

Albuquerque, NM, United States of America

Ronald L Cline