3 Com Corporation

Texas Instruments Corporation

3com Corporation

Ronald Joseph Sullivan

Brett Walter Chaveriat

Ron Rotstein

Robert C Suffern

Daniel G Prysby

Khodor S Elnashar

Michael John Zroka

A system linking a serial interface with a processor that is parallel in nature is described. A system memory having a receive buffer stores data from a UART destined for processing by a central processing unit. A control state machine interrupts the central processing unit to initiate processing of the data in the receive buffer when the receive buffer reaches a certain state, such as storing a full frame of data. Command characters indicative of control conditions in the data stream are detected by discrete hardware in a receive command processor, and the memory address in the receive buffer is forwarded to the central processing unit. The resulting system substantially improves the speed and efficiency of the transfer of data between the UART and the central processing unit.

Memory based buffering for a UART or a parallel UART like interface

A method and apparatus for compensating for input threshold variations in input buffers is provided. The method and apparatus compensate for input threshold variations by applying a bias voltage on a known capacitance of an RC calibration circuit using, for example, a pulse width modulator. The bias voltage helps ensure that the time to charge the known capacitance from the bias voltage to the input threshold voltage of the input buffer is independent of the threshold voltage. The bias voltage is chosen using an iterative process in which the time to charge from the bias voltage to the threshold voltage is compared with a reference time. The bias voltage is adjusted based on the comparison.

Method and apparatus for compensating input threshold variations on input buffers

A behavioral language-based methodology for the verification and testing of digital circuit designs. An automated or interactive simulation verification system can be used in accordance with the methodology to verify a digital circuit on inexpensive, simple digital circuit simulators, using behavioral languages, and achieve certain performance features found only on more costly, complex simulators.

Behavioral language models for testing and verification of digital

A processor on an add-on card that arbitrates demand on a memory unit on the add-on card. The processor and memory unit are used for the underlying functionality of the add-on card. The processor determines an appropriate time to allow interface operations to the memory unit when the memory unit is not already being accessed for the underlying functionality of the card. By using the processor and memory unit on the add-on card for interface operations to the host computer, the add-on interface circuitry on the add-on card can be minimized and simplified.

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Elgin, IL, United States of America

Ronald Joseph Sullivan