International Business Machines Corporation

Ronald James Chapman

Gary William Batchelor

Michael T Benhase

Carl Evan Jones

Kenneth Wayne Todd

Cheng-Chung Song

Sushama M Paranjape

Ariel Brent Christensen

A trace information queueing system receives a plurality of trace information signals and transmits them through a common connector. The multiple trace information signals may be multiplexed. Each edge of a clock signal may be used to enable transmission of different trace information signals. Alternatively, separate clocks signals may be provided for each trace information signal. A programmable logic device may be used to both multiplex the trace information signals and produce the clock signals necessary to enable their transmission.

Trace information queueing system

A method of verifying the passage of a data write across a bus is provided including sending the data write from an originator across the bus to a target, counting the number of data entries received at the target with a counter, and transmitting a return echo write from the target across the bus to a return address. The method further includes attaching the counter value to other data associated with the return echo write and polling the return address. The method allows determination of the completion of a data write by comparing the number of data entries included in the data write with the counter value polled from the return address. Alternatively, in a data streaming environment the progress of a data write may be determined by comparing the number of data entries included in the data write at a select point in time with the counter value polled from the return address. Typical data entries which are counted may include, but are not limited to, bytes, words, double words, or similar data quantities.

Method and system for performance enhancement via transaction verification using a counter value in a polled data storage environment

Data management systems, such as used in disk control units, employ memory entry lists to help keep track of user data. Improved performance of entry list maintenance is provided by the present invention. Much of the protocol employed to conduct such maintenance is preferably performed by hardware-based logic, thereby freeing other system resources to execute other processes. New entries to the memory list are only allowed at predetermined addresses and entries are updated by writing a predetermined data pattern to a previously allocated address. Optionally, improved error detection, such as a longitudinal redundancy check, may also be performed in an efficient manner during entry list maintenance to assure the integrity of the list.

Efficient maintenance of memory list

An improved multi-bit error correction system. The inventive error correcting system performs a fast error correction operation on individual bits within multi-bit modules. In a specific implementation, the invention uses Hamming codes and divides an n times m bit data word into m modules, with each module having n bits. Next, the ith bits of each module are combined to form a set of parity bits. Syndrome bits are generated from the parity bits and used to locate errors in the bits and provide an indication of same. Finally, errors in the bits are corrected in a conventional manner to provide corrected data bits.

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Tucson, AZ, United States of America

Ronald James Chapman