Texas Instruments Corporation

Ronald J Syzdek

Sung-Wei Lin

Brian L Brown

Tim M Coffman

Jackson Leung

Pow Cheah Chang

Phat C Truong

Timothy J Coots

Ming-Bo Liu

A semiconductor memory device ( ) having a parallel test circuit is disclosed. A test data path ( ) receives parallel I/O line (I/O -I/O ) values, and generates therefrom test result data values (PASS and DATA_TST). The test result data values (PASS and DATA_TST) are coupled to a gate control circuit ( ). The gate control circuit ( ) provides either a first logic value, a second logic value, or an intermediate logic value to an open drain output driver ( ) depending upon the test result data values (PASS and DATA_TST). In response to the logic values received from the gate control circuit ( ), the open drain output driver ( ) drives a data output (DQ) to a first, second or intermediate logic level.

Current controlled multi-state parallel test for semiconductor device

A semiconductor memory device ( ) having a parallel test circuit is disclosed. A test data path receives parallel I/O line (I/O -I/O ) values, and generates therefrom test result data values (PASS and DATA_TST). The test result data values (PASS and DATA_TST) are coupled to a two-bit register ( ) and output in a sequential fashion to an open drain output driver ( ). In this manner, test result data values are provided by driving an output (DQ) in a rapid sequential fashion, rather than placing the output at one of three states (such as logic high state, a logic low state, or a high impedance state).

Two pass multi-state parallel test for semiconductor device

A supply-voltage detecting stage (11) that supplies first and second reference currents (I.sub.REFP and I.sub.REFN) which vary with the supply voltage (V.sub.cc) and are coupled by first and second gain stages (12A and 12B), respectively, to first and second temperature-detecting stages (13A and 13B), respectively. First and second temperature-detecting stages (13A and 13B) increase the coupled reference currents (I.sub.REFP and I.sub.REFN), respectively, to compensate for temperature increase through use temperature-sensitive, long-channel transistors (M34-M37 and M42-M45), supplying temperature and supply-voltage compensated output bias voltages at output terminals (MIRN and MIRP).

Temperature and supply-voltage sensing circuit

The method of this invention prevents transient currents at high-frequency disable cycles and disables DC current paths after a minimum delay time, thereby reducing power dissipation. This invention includes a delay circuit functioning to prevent disablement of DC paths where chip-disable times occur at intervals below a minimum duration. The result is a decrease in the number of undesired voltage drops on internal power buses due to transient currents. The method detects external chip-disable pulses that occur before a minimum time duration, then prevents those pulses from powering down internal direct-current paths. At the same time, the output driver high impedance functionality of the chip-disable signal is preserved.

Memory device performance by delayed power-down

The circuit of this invention improves significantly the programming speed of a Flash EPROM. The circuit includes a detector circuit (DC) using a pre-charge capacitor (C1), capacitor dividers [(C1/(C1+C2) and C3/(C2+C3)] and a voltage comparator (COMP) to signal a control logic circuit (CLC) when the programming voltage is within supply voltage (V.sub.cc) of its final value. At that point the control logic circuit (CLC) boosts the voltage on one terminal of a boost capacitor (BC) by the value of the supply voltage (V.sub.cc). The other terminal (XDD) of the boost capacitor (BC) furnishes the boosted programming voltage for the Flash EPROM.

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Sugar Land, TX, United States of America

Ronald J Syzdek