Freescale Semiconductor,inc.

Nxp USA, Inc.

Ronald J Syzdek

Jeffrey C Cunningham

Gilles Muller

Cheong Min Hong

Gowrishankar L Chindalore

Richard Eguchi

Karthik Ramanan

Thomas Jew

Ross Sinclair Scouller

Horacio P Gasquet

Peter J Kuhn

Sung-Taeg Kang

Brian A Winstead

Frank Kelsey Baker, Jr

Jane A Yater

Chen He

Fuchen Mu

Xiaojie He

David W Chrudimsky

Paul A Ingersoll

Thomas D Cook

Timothy J Strauss

Tahmina Akhter

Stephen F McGinty

Marco A Cabassi

Gilles J Muller

Horatio P Gasquet

A memory includes a row decoder that receives an address of a row to be read and an operand. The memory includes a memory array of bitcells that can be configured to store N-bit weight values in which N is an integer greater than one. The row decoder is configured to, for a multiplication mode read operation at the selected word line, selectively activate the selected word line based on a bit value of the received operand to selectively read an N-bit weight value based on a bit value of the operand. Such an operation may in some embodiments, perform a multiplication operation of the bit value of the operand and the N-bit weight value.

Memory reads of weight values

A memory is provided. The memory includes an array of non-volatile memory (NVM) cells arranged in a plurality sectors. A control gate driver circuit has an output coupled to control gates of the NVM cells in a sector in the plurality of sectors. An address decoder is coupled to the control gate driver circuit. And a latch circuit is coupled between the address decoder and the control gate driver circuit. The latch circuit stores a first value, and based on the stored first value, the control gate driver circuit output is floating.

Split-gate memory having sector retirement with reduced current and method therefor

A split gate memory array includes a first row having memory cells; a second row having memory cells, wherein the second row is adjacent to the first row; and a plurality of segments. Each segment includes a first plurality of memory cells of the first row, a second plurality of memory cells of the second row, a first control gate portion which forms a control gate of each memory cell of the first plurality of memory cells, and a second control gate portion which forms a control gate of each memory cell of the second plurality of memory cells. The first control gate portion and the second control gate portion converge to a single control gate portion between neighboring segments of the plurality of segments.

Scalable split gate memory cell array

A memory system has an array of split gate non-volatile NVM cells that are in program sectors and the program sectors make up one or more erase sectors. The control gate of cells in a program sector are physically connected. A program/erase circuit programs a selected program sector by applying a programming signal to the control gates of the split gate memory cells of the selected program sector while applying a non-programming signal to the control gates of program sectors not selected for programming, that erases an erase sector comprising a plurality of the program sectors by contemporaneously applying an erase voltage to the control gates of the split gate NVM cells of the erase sector, wherein during the applying the programming signal, the program/erase circuit applies a source voltage to the sources of each of the split gate NVM cells of the erase sector.

Common source architecture for split gate memory

A circuit includes a non-volatile memory, a calibration circuit, and a sense amplifier. The sense amplifier senses a state of a memory cell during sensing. The sense amplifier includes a differential circuit having a first input coupled to a reference current source, a second input, and an output coupled to the calibration circuit during a calibration mode. A calibration current source is configured to be coupled to the second input of the differential current sensing circuit during the calibration mode and decoupled from the second input during the sensing mode. A variable current source is coupled to the differential current sensing circuit and the calibration circuit. The calibration circuit tests a plurality of currents of the variable current source during the calibration mode and selects one of the plurality of currents. The sense amplifier senses using the selected one of the plurality of currents.

Multibit sense amplifier calibration

A non-volatile memory (NVM) system has a normal mode, a standby mode and an off mode that uses less power than the standby mode. The NVM system includes an NVM array that includes NVM cells and NVM peripheral circuitry. Each NVM cell includes a control gate. A controller is coupled to the NVM array, applies a voltage to the control gates and power to the peripheral circuitry during the standby mode, and applies an off-mode voltage to the control gates and removes power from the NVM peripheral circuitry during the off mode.

Biasing split gate memory cell during power-off mode

A semiconductor memory device includes a non-volatile memory, a memory controller, and a charge pump system. The memory controller establishes first parameters for a first programming cycle of a first plurality of memory cells of the non-volatile memory prior to the first programming cycle being performed. The charge pump system includes a plurality of charge pumps and provides a first programming pulse for use in performing the first program cycle. The first programming pulse is provided by selecting, according to the first parameters, which of the plurality of charge pumps are to be enabled during the first program cycle and which are to be disabled during the first program cycle.

Smart charge pump configuration for non-volatile memories

Methods and systems are disclosed for sector-based regulation of program voltages for non-volatile memory (NVM) systems. The disclosed embodiments regulate program voltages for NVM cells based upon feedback signals generated from sector return voltages that are associated with program voltage drivers that are driving program voltages to NVM cells within selected sectors an NVM array. As such, drops in program voltage levels due to IR (current-resistance) voltage losses in program voltage distribution lines are effectively addressed. This sector-based regulation of the program voltage effectively maintains the desired program voltage at the cells being programmed regardless of the sector being accessed for programming and the number of cells being programmed. Sector return voltages can also be used along with local program voltages to provide two-step feedback regulation for the voltage generation circuitry. Test mode configurations can also be provided using test input and/or output pads.

Sector-based regulation of program voltages for non-volatile memory (NVM) systems

A memory having an array of multi-gate memory cells and a word line driver circuit coupled to a sector of memory cells of the array. In at least one mode of operation, the word line driver circuit is controllable to place an associated control gate word line coupled to the control gate word line driver and coupled to the sector in a floating state during a read operation where the sector is a non selected sector.

Control gate word line driver circuit for multigate memory

A method of programming a split gate memory applies voltages differently to the terminals of the selected cells and the deselected cells. For cells being programming by being coupled to a selected row and a selected column, coupling the control gate to a first voltage, coupling the select gate to a second voltage, programming is achieved by coupling the drain terminal to a current sink that causes the split gate memory cell to be conductive, and coupling the source terminal to a third voltage. For cells not being programmed by not being coupled to a selected row, non-programming is maintained by coupling the control gate to the first voltage, coupling the select gate to a fourth voltage which is greater than a voltage applied to the select gate during a read in which the split gate memory cells are deselected but sufficiently low to prevent programming.

Programming a split gate bit cell

A configurable multistage charge pump including multiple pumpcells, at least one bypass switch and control logic. The pumpcells are coupled together in series including a first pumpcell receiving an input voltage and at least one remaining pumpcell including a last pumpcell which generates an output voltage. Each bypass switch is coupled to selectively provide the input voltage to a pumpcell input of a corresponding one of the remaining pumpcells. The control logic is configured to determine one of multiple voltage ranges of the input voltage, to enable each pumpcell for a first voltage range and to disable and bypass at least one pumpcell for at least one other voltage range. A method of operating a multistage charge pump including detecting an input voltage, selecting a voltage range based on an input voltage, and enabling a number of cascaded pumpcells corresponding to the selected voltage range.

Configurable multistage charge pump using a supply detect scheme

A method and memory are provided for determining a read reference level for a plurality of non-volatile memory cells. The method includes: performing a program operation of the plurality of non-volatile memory cells; determining a program level of a least programmed memory cell of the plurality of memory cells; performing an erase operation of the plurality of non-volatile memory cells; determining an erase level of a least erased memory cell of the plurality of memory cells; determining an operating window between the program level and the erase level; and setting the read reference level to be a predetermined offset from the erase level if the operating window is determined to compare favorably to a predetermined value. The memory includes registers for storing the program level and the erase level.

Read conditions for a non-volatile memory (NVM)

A first value from a set of bit cells of a sector of a non-volatile memory device is sensed based on a first read reference. A second value from the set of bit cells is sensed based on a second read reference different than the first read reference. A third read reference for a first subsequent access to the sector of the non-volatile memory device is determined based on at least one of the first read reference and the second read reference in response to determining a first error code condition associated with the first value and a second error code condition associated with the second value represent different error code conditions.

Memory device with adjustable read reference based on ECC and method thereof

A method including performing a program/erase cycle on a first non-volatile memory (NVM) bit of an integrated circuit using a first fluence, wherein the first NVM bit has a first transconductance is provided. The method further includes performing a program/erase cycle on a second NVM bit of the integrated circuit using a second fluence, wherein the second NVM bit has a second transconductance, and wherein the first transconductance is greater than the second transconductance and the second fluence is greater than the first fluence.

Non-volatile memory with reduced charge fluence

An integrated circuit memory has a plurality of non-volatile memory cells and a reference cell. The reference cell provides a reference current for reading a selected memory cell of the plurality of non-volatile memory cells. A method comprises trimming the reference cell to a predetermined threshold voltage, wherein trimming the reference cell comprises biasing a control gate, a source terminal, a drain terminal, and a substrate terminal of the reference cell with a predetermined set of bias conditions, wherein in response to the predetermined set of bias conditions, the reference cell will gain or lose charge toward an asymptotic state of charge that no longer changes significantly after a predetermined operating time under the predetermined set of bias conditions. In addition, the integrated circuit memory is also configured to adjust the reference cell gate voltage to output a desired target current reference.

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Austin, TX, United States of America

Ronald J Syzdek