At&t Bell Laboratories

Other

Infineon Technologies Ag

American Telephone & Telegraph Co., At&t Bell Laboratories

International Business Machines Corporation

Siemens Aktiengesellschaft

Infineon Technologies LLC

Ronald J Schutz

Ravikumar Ramachandran

Alexander William Simpson

Nadia Lifshitz

Vivian W Ryan

Jeffrey P Gambino

Jack Allan Mandelman

Laertis Economikos

Chandrasekhar Narayan

Andreas Knorr

Dirk Tobben

Hua Shen

Jenny Lian

Joseph M Moran

Ruichen Liu

Chenting Lin

Kenneth C Arndt

Rainer F Schnabel

Haruki Nojo

Kin Ping Cheung

Gerald Smolinsky

Keith K Wong

Sumit Pandey

Pang-Dow Foo

Edward P Martin, Jr

Richard S Wagner

Avid Kamgar

Frank B Alexander, Jr

Christopher J Case

Peter A Heimann

Gregory M Gutt

Robert V Knoell

An advantageous optical apparatus with relatively large field viewing of an image to the rear of an observer is disclosed. The apparatus has two mirrors having cylindrical symmetry where the mirrors are positioned so that a plane of symmetry for each mirror is substantially coincident. The mirrors are further configured so that the apparatus has an astigmatism less than 0.0035, and a ratio between the far field and the near field magnification of less than 0.9. The apparatus is fabricated, in one embodiment, by using force to conform a thin polymer mirror onto an appropriate surface configuration on a monolithic block.

Optical device with two cylindrically symmetric mirrors

A polyelectrolyte dispensing polishing pad, a process for its production and a method of polishing, e.g., chemical mechanical polishing (CMP), a substrate such as a semiconductor wafer, are provided. The pad is usable for CMP planarization of an oxide or metal layer on the wafer. The pad has a polishing layer of erodible binder material containing uniformly distributed therein both abrasive particles and a water soluble ionizable electrolyte substance such as a polyelectrolyte, such that during polishing the binder material incrementally erodes and the abrasive particles and electrolyte substance incrementally release into direct contact with the substrate. The electrolyte substance inhibits CMP removal of silicon nitride, e.g., as a stop layer, under an upper oxide or metal layer, such that the upper layer is selectively polished and the CMP stops on the stop layer leaving the latter intact.

Polyelectrolyte dispensing polishing pad

Polyelectrolyte dispensing polishing pad, production thereof and method of polishing a substrate

A method of forming an integrated barrier/contact for stacked capacitors is provided which results in reduced cost of ownership and in a barrier which is nominally several times thicker than convention structures. The resulting structure results in decreased contact plug resistance as compared with conventional devices.

Method for forming an integrated barrier/plug for a stacked capacitor

The invention provides slurry-less chemical-mechanical polishing processes which are effective in planarizing oxide materials, especially siliceous oxides, even where the starting oxide layer has significant topographical variation. The processes of the invention are characterized by the use of a fixed abrasive polishing element and by use of an aqueous liquid medium containing a cationic surfactant for at least a portion of the polishing process involving reduction in the amount of topographic variation (height differential) across the oxide material on the substrate. The method reduces or eliminates the transfer of topographic variations to levels below the desired planarization level.

Slurry-less chemical-mechanical polishing of oxide materials

An aqueous slurry-less composition for chemical-mechanical-polishing of a silicon dioxide workpiece comprising: a cationic surfactant that is soluble and ionized at neutral to alkaline pH conditions, in which the cationic surfactant is present in an aqueous slurry-less composition in an amount less than its critical micelle concentration.

Compositions for and method of reducing/eliminating scratches and defects in silicon dioxide during CMP process

A method for enhancing the removal rate of a metal barrier layer during CMP includes providing a semiconductor wafer having an insulator layer, a metal barrier layer formed on at least a portion of the insulation layer and a conductive layer formed thereon and contacting the semiconductor wafer with a chemical-mechanical polishing slurry containing a metal removal-enhancing amount of at least one chelating agent.

Methods for enhancing the metal removal rate during the

A semiconductor structure comprising a semiconductor substrate, an electrically conductive level on the substrate and a metal fuse located at the conductive level wherein the fuse comprises a self-aligned dielectric etch stop layer thereon is provided along with processes for its fabrication.

Semiconductor structure including a conductive fuse and process for

Stress induced grain boundary movement in aluminum lines used as connections in integrated circuits is substantially avoided by doping the aluminum with iron. Through this expedient not only is grain boundary movement avoided but electromigration problems are also decreased.

Aluminum metallization doped with iron and copper to prevent

In some circuitry, field effect transistors are produced by employing polycrystalline conductive regions including the channel and connections to the source and drain. Conventional methods for producing such transistors involve depositing a thin polycrystalline channel region, patterning this region overlying the patterned region with an insulator, producing openings in the insulator for contacts to source and drain, and depositing a thick polycrystalline contact region. Processing complexity is, however, substantially reduced by first forming interconnect areas, source region and drain regions; then opening a region for the channel; and finally depositing a layer to form the channel. Thus, at least three processing steps are eliminated and vertical dimensions are reduced.

Fabrication method in vertical integration

For integrated circuit devices with strict design rules, junctions defining the source and drain are typically more shallow than 0.25 .mu.m and are made through vias having an aspect ratio greater than 1.1. Suitable electrical contact to such a shallow junction is quite difficult. To ensure an appropriate contact, an adhesion barrier layer such as titanium nitride or an alloy of titanium and tungsten is first deposited. Tungsten is then deposited under conditions which produce a self-limiting effect in a prototypical deposition on silicon. Additionally, these tungsten deposition conditions are adjusted to higher rather than lower deposition temperatures. Subsequent deposition of aluminum if desired, completes the contact.

Process for fabricating integrated circuits having shallow junctions

Disclosed is a method for manufacturing an integrated circuit which includes the step of evaluating the reliability of metal films in the circuit using a noise measurement technique. In one embodiment, a film portion to be tested is incorporated in a Wheatstone bridge. A relatively large direct current is passed through the film to stimulate 1/f.sup.2 noise. A relatively small alternating current is concurrently passed through the film. The bridge imbalance signal at the ac frequency is amplified and demodulated by a phase-locked amplifier, and is then frequency analyzed. The film is evaluated by comparing the resulting noise power spectrum with predetermined standards.

Method for reliability testing integrated circuit metal films

Direct contact to shallow junctions in integrated circuits and interconnection between these contacts is achievable by utilizing a specific aluminum CVD process. In this process the aluminum is deposited utilizing a triisobutyl aluminum precursor onto a substrate having a nucleation layer, e.g. a titanium nitride layer. By appropriate choice of this nucleation layer to control the nucleation of the depositing aluminum, suitable contact is made while avoiding void defects present in the absence of such layer.

Smoothing irregularities in a surface is accomplished by a wet-etchback technique. In this technique, a polysilicate composition is formed on a nonplanar substrate such as the surface of an integrated-circuit wafer. The polysilicate is etched away and the etching is continued into the underlying surface. As a result, a substantial smoothing of the surface is obtained.

Fabrication of devices utilizing a wet etchback procedure

Stress induced grain boundary movement in aluminum lines used as connections in integrated circuits is substantially avoided by doping the aluminum with iron. Through this expedient not only is grain boundary movemenmt avoided but electromigration problems are also decreased.

Growing community of inventors

Warren, NJ, United States of America

Ronald J Schutz