International Business Machines Corporation

Ronald J Prilik

George Frederick Walker

Charles Hampton Perry

James Marc Leas

David Lewis Gardell

Jody John Van Horn

Robert William Koss

Steve Leo Dingle

Michael Richard Ouellette

Donald Lawrence Wheater

R Dean Adams

Pamela Sue Gillis

Ernest H Millham

Kevin William McCauley

Francis Woytowich

James R Varner

Steven H Foreman

James E Ortloff

Michael S Dampier

Norman R Rapoport

An apparatus and a method for simultaneously testing or burning in all the integrated circuit chips on a product wafer. The apparatus comprises a glass ceramic carrier having test chips and means for connection to pads of a large number of chips on a product wafer. Voltage regulators on the test chips provide an interface between a power supply and power pads on the product chips, at least one voltage regulator for each product chip. The voltage regulators provide a specified Vdd voltage to the product chips, whereby the Vdd voltage is substantially independent of current drawn by the product chips. The voltage regulators or other electronic means limit current to any product chip if it has a short. The voltage regulator circuit may be gated and variable and it may have sensor lines extending to the product chip. The test chips can also provide test functions such as test patterns and registers for storing test results.

Semiconductor wafer test and burn-in

A method and apparatus for testing a semiconductor chip includes providing the semiconductor chip with a common input/output (I/O) or bidirectional I/O pad. The I/O pad is electrically coupled to an off-chip driver (OCD) and an off-chip receiver (OCR). The OCD, I/O pad, and OCR are combined in a common input/output (CIO) or bidirectional I/O configuration. The I/O pad is effectively open circuited by an external tester and a performance parameter of the IO circuits connected to the open circuited pad is tested.

Self-timed AC CIO wrap method and apparatus

A built-in self-test (BIST) apparatus and method for testing an integrated circuit are disclosed which enable capture of failure data for a selected failure. The BIST apparatus comprises a clock generator, which generates at least a first clock signal, and a built-in self-tester, which applies predetermined input data patterns to the integrated circuit in response to the first clock signal. In addition, the BIST apparatus includes a data comparator for comparing output data received from the integrated circuit with expected output data. The data comparator detects a failure within the integrated circuit when the output data received from the integrated circuit differs from the expected output data. The BIST apparatus further includes a clock controller that disables the first clock signal in response to the detection of a selected occurrence of a failure. By enabling testing of the integrated circuit to be halted upon the occurrence of a selected failure, failure analysis of the integrated circuit is enhanced.

Method and built-in self-test apparatus for testing an integrated

A printed circuit board especially for use in device testing apparatus is provided. The circuit board includes a plurality of stacked layers of dielectric or insulating material with each of the layers having coated on one surface thereof a layer of conducting material defining a plane. The conducting material extends to at least one outer edge of the stack of the material for each plane and at each plane it is spaced with respect to the outer edge locations of all of the other planes. A plurality of lands extend vertically along the stack of material, each land while extending the entire length, only contacting the plane of conducting material extending to the edge at the location of the land whereby a signal applied to any given land is conducted only on the planes where that plane extends to the surface. The configuration for a testing device preferably is an annular configuration and the planes of conducting material extend to both the inner and outer surfaces and signals are applied to the outer surface from an external source and delivered to the test piece from the inner surface.

Multi-layer printed circuit board

A memory array device with an embedded self-test binary pattern. The device has an array of bistable cells formed with first and second sides that are oppositely connected to a first voltage line or a second voltage line. If the first and second voltage lines are energized at the same voltage level, each of the bistable cells will function in a normal bistable mode. If the first and second voltage lines are energized at different levels, each of the bistable cells will function in an embedded binary pattern mode.

Read/write memory device with an embedded read-only pattern and method

A tester for logic circuits provided with a fast recovery power supply for supplying high current to a logic circuit under test and for measuring a low current of the circuit under test. The power supply of the tester has first and second amplifiers coupled to the CMOS circuit being tested and having dual feedback loops with one loop controlling the resistance of the other loop. The first amplifier is coupled between a reference voltage and a capacitor supplying current to the CMOS circuit under test. The second amplifier is coupled between the same reference voltage, and the output of the first amplifier. A resistive feedback is coupled between the circuit under test and the output of the first amplifier and an AC coupled impedance switching means is coupled between the output of the second amplifier and across the resistive feedback whereby the impedance switch can alter the impedance of the resistive feedback by shunting the resistor to recharge the capacitor supplying current to the circuit under test.

Fast recovery power supply

Logic and analog functions in a complex semiconductor component are stuck fault and parametrically tested through an analog/digital measurement adapter coupled to logic and analog testers. Both logic and analog testers are under computer control whose purpose is to direct the testing sequence, log test results, perform algorithmic calculations on the data and diagnose failing devices in the component under test. The adapter provides the electrical environment to match a range of components under test to the logic and analog testers. The adapter is also under computer control to permit impedance matching of a multiplicity of digitally controlled stimulus/response units connected through a multiplexor to the range of components under test.

Automatic tester for complex semiconductor components including

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Chesterfield, VA, United States of America

Ronald J Prilik