Teraconnect, Incorporated

Ronald J Olson, Jr

Richard J Williams

Gregory K Duddoff

An optical array chip ( ) is flip-chip bonded to ASIC substrate ( ), and electrically connected to its supporting circuitry through compressively joined solder bump sets ( ) and ( ). Flowable epoxy hardener material ( ) is applied to underfill between the surfaces of chip ( ) and the ASIC surface, surrounding the bump contact sets and filling a standoff cavity system that had been etched in the electrical interface side of chip ( ) to a depth greater than electrical layer ( ) of chip ( ) by the amount of the pre-determined standoff height, prior to application of its bump contacts. Standoff grid ( ) and individual optical devices ( ) are exposed after lapping and etching of the optical interface side of chip ( ) down to the level of electrical layer ( ). The grid structure may have other forms, such as a vertical perimeter standoff ridge surrounding chip ( ) or penetrating electrical layer ( ), or a distributed pattern of vertical posts or wall sections penetrating electrical layer (66).

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Amherst, NH, United States of America

Ronald J Olson, Jr