Digital Equipment Corporation

Ronald J Melanson

Ji L Yang

Paul Michael Guglielmi

Alan Kotok

A current mode logic circuit which is implemented with metal-semiconductor field effect transistors (MESFETs) has a triggering circuit which produces hysteresis in the output of the circuit. That is, the output switches abruptly after the input has almost completed a corresponding transition from one logical output to another in a manner characteristic of triggering circuits such as Schmidt triggers. A triggering voltage is generated in response to one of two complementary outputs by triggering transistors configured as a current switch. The triggering voltage delays switching of a logic switching circuit which produces the two outputs which are a logical or boolean function of the input or inputs. The MESFETs are implemented in gallium arsenide technologies and output is equal to the inverted input.

Current mode logic switching circuit having a Schmitt trigger

A semiconductor buffer circuit and buffering method for driving capacitive loads that enhances the current sinking and sourcing drive characteristics at times when the input signal is changing. Two transistors are used, a source follower and a current source pull-down, with an input signal applied to the control input of the source follower transistor. The complement of the input signal is capacitively coupled to the control input of the current source pull-down transistor. As a result, changes in the input voltage increase or decrease the conductivity of the current source pull-down transistor, thereby allowing the capacitive load to be charged and discharged more efficiently.

Apparatus and method for capacitor coupled complementary buffering

A self-timed random access memory circuit is designed on a single monolithic integrated circuit chip. The chip includes a random access memory including addressable storage locations, address decoding circuitry, data input and output circuitry and write enable circuitry. In addition, the chip includes input latches connected to chip input terminals which store data, address and operation control signals from off-chip circuitry in response to a timing signal, also from the off-chip circuitry. Also in response to the timing signal, an output latch on the chip stores data from the random access memory for transmission to output terminals, where the data is available to the off-chip circuitry. The input and output latches permit the self-timed random access memory circuit to perform in a pipelined manner. In addition, the chip includes circuitry that generates the control signals, in response to the latched control signals, with the correct timing for controlling the random access memory, obviating the necessity of the system designer designing a system including the chip having to design off-chip control circuitry with the required timing.

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Sunnyvale, CA, United States of America

Ronald J Melanson