Sun Microsystems, Inc.

Oracle America, Inc.

Ronald J Melanson

Aleksey M Urmanov

David K McElfresh

Anton A Bougaev

Sorin Iacobovici

Kenneth Clayton Gross

David J Greenhill

Chakra R Srivatsa

Renu Raman

Greg Papadopoulos

Some embodiments of the present invention provide a system that includes a first hard disk drive (HDD) and a second HDD. Within this system, the first HDD is coupled to the second HDD in a non-parallel configuration, which reduces rotational vibration transmitted between the first HDD and the second HDD.

Method and apparatus for reducing coupled hard disk drive vibration

A random access memory includes a first memory bank, a second memory bank, an error checking circuit operatively connected to receive data read from the first memory bank, and a multiplexer operatively connected to input data read from both the first memory bank and the second memory bank, wherein input selection of the multiplexer is controlled by an output of the error checking circuit. A method for reducing errors in a memory system includes writing data into first and second memory banks of the memory system in parallel, reading data from a desired location of the first memory bank, checking the data read from the first memory bank for errors, if no errors are present, outputting the data read from the first memory bank to a bus, and if the data read from the first memory bank contains errors, outputting data read from a parallel location in the second memory bank to the bus. A method for reducing errors in a memory system comprises writing data into first and second memory banks of the memory system in parallel, reading data from a desired location of the first memory bank, checking the data read from the first memory bank for errors, if no errors are present, outputting the data read from the first memory bank to a bus, and if the data read from the first memory bank contains errors, outputting data read from a parallel location in the second memory bank to the bus.

Partitioned random access memory

A power dissipation control mechanism for a central processing unit includes a power estimation circuit for estimating the power dissipation of instructions executed by the central processing during a selected time interval and a speed controller for adjusting the speed of the central processing unit in response to the estimated power dissipation produced by the power estimation circuit.

Microprocessor speed control mechanism using power dissipation estimation based on the instruction data path

Circuits and methods for eliminating hold time violations are disclosed. A DE-type flip-flop latches a data input signal on a data input terminal a fraction of a clock period before a triggering edge of the clock signal. The DE-type flip-flop provides a data output signal for a full clock period beginning after the triggering edge of the clock signal. The DE-type flip-flop includes a latch having its data output terminal coupled to the data input terminal of a flip-flop. The flip-flop clock input pin and the latch enable terminal of the latch are connected to a clock line. The DE-type flip-flop used in place of a standard flip-flop, in which a hold time violation occurs, eliminates the hold time violation.

Method and circuit for eliminating hold time violations in synchronous

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Woodside, CA, United States of America

Ronald J Melanson