Honeywell G.m.b.h.

Honeywell International Inc.

Motorola Corporation

Ronald J Freimark

Jay William Gustin

Tony J Kozlik

Elliott H Rachlin

Donald W Moore

Jiandong Huang

Mark L Shaw

Laurence A Clawson

Michael L Hodge

Sejun Song

William L Call

Steven A Rose

Paul McGaugh

Steven C Ramsdell

Paul S Connolly

A computer apparatus that interconnects a standard commercial off the shelf (COTS) computer to a proprietary system. The standard COTS computer replaces a proprietary computer and assumes its roles of controlling a workstation and a display thereof of the proprietary system. The computer apparatus comprises a frame that carries the COTS computer, a power converter, adapters, a video module, Ethernet and UBS connectors, a hard drive and the like. The frame mates with slots of a backplane of the proprietary system.

Computer apparatus for interconnecting an industry standard computer to a proprietary backplane and its associated peripherals

The present invention provides a method and apparatus for facilitating communication with non-fault tolerant network nodes in a fault-tolerant network environment. In various embodiments, a network address or network location of any network nodes present on a network that are not fault-tolerant is determined and stored, and data intended for the detected non-fault-tolerant network nodes is routed only over that network to which the non-fault-tolerant network node is connected. In further embodiments, the fault-tolerant network comprises a primary and redundant network with fault tolerant network nodes that are attached to each network; a non-fault-tolerant network node that is attached to either the primary or redundant network is then operable to communicate with any fault-tolerant network node via data sent over only the network to which the non-fault-tolerant network node is connected.

Non-fault tolerant network nodes in a multiple fault tolerant network

A system for, and method of, emulating, on a non-native computer, a native environment for a visual display object file for a real time process control system and a real time process control system employing the emulator. The visual display object file contains a drawing command, an address pointer for communicating data with the real time process control system and a rule for interpreting data received from a touch-sensitive screen. The system includes: (1) a display routine that causes the non-native computer to control a non-native visual display coupled thereto to display an image thereon as a function of the drawing command, (2) an address mapping routine that communicates the data between the visual display object file and the real time process control system as a function of the address pointer and (3) an input translation routine that translates data received into the non-native computer from a non-native pointing device coupled thereto into data suitable for interpretation by the rule, the system thereby allowing the non-native computer to display the image, communicate the data with the real time process control system and interpret the data received from the non-native pointing device.

Emulator for visual display object files and method of operation thereof

An apparatus controls the movement of a data block between a peripheral and a data processing system, which comprises a bus which includes an address bus, a first data bus, and a second data bus, the peripheral being connected to the second data bus. A first memory, connected to the second data bus, stores data, and a second memory, connected to the first data bus, stores a plurality of dummy routines in predetermined areas, the predetermined areas of the second memory having corresponding buffer areas in the first memory. The first memory and the second memory correspond to a first memory area and a second memory area within a total predefined memory space, each memory location within the total memory space being defined by a unique memory space address. A processor connected to the first data bus, fetches an instruction, in response to a control signal from the peripheral, from a preselected one of the dummy routines. The address of the instruction is placed on the address bus specifying a corresponding location of the corresponding buffer area in the first memory. A switch element connected to the first data bus and the second data bus, disconnects the first data bus from the second data bus in response to an enable signal. Logic circuitry generates at least one control signal in response to the fetching of the instruction from one of the dummy routines, such that data is transmitted between the peripheral and the data processing system.

Microprocessor assisted data block transfer apparatus

An apparatus for controlling data movement between a peripheral and a data processing system, comprises a memory for storing data, wherein the memory comprises a plurality of memory modules. Each memory module corresponds to an assigned area of a first memory map, the first memory map being duplicated into a plurality of mirrored memory maps. Each mirrored memory map corresponds to a predefined operation, a composite of the first memory map and the plurality of mirrored memory maps forming a total memory space. Each memory location within the total memory space is defined by a unique memory space address. A processor performs a pseudo operation in response to a first control signal from the peripheral indicating data is available for being moved. A logic circuit generates at least one control signal in response to the pseudo operation such that a predetermined data movement operation occurs.

Microprocessor assisted memory to memory move apparatus

An amplifier circuit is disclosed for temperature compensating the output voltage thereof with respect to undesirable temperature induced signals from a silicon pressure transducer and/or from components of the amplifier itself. The amplifier includes a first operational amplifier and a second operational amplifier. A first circuit connects the output terminal of the first operational amplifier through a summing node to one input terminal of the second amplifier. Output signals from the pressure transducer are applied between one input terminal of the first operational amplifier and another input terminal of the second amplifier. A temperature compensating circuit is connected to the summing node for enabling the output voltage of the amplifier to be substantially independent of temperature. An initial offset voltage compensating circuit is coupled to the summing node for adjusting the intercept of the pressure-to-output voltage transfer curve. The gain of the second operational amplifier determines the slope of the curve.

Temperature compensating pressure sensor amplifier circuits

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Scotsdale, AZ, United States of America

Ronald J Freimark