Lucent Technologies Inc.

Cadence Design Systems, Inc.

Ronald H Hardin

Robert Paul Kurshan

Ravi Prakash

Alok Jain

Xiaoqun Du

Manu Chopra

Kavita Ravi

Pratik Mahajan

A method and system for verifying integrated circuit designs through partitioning. In an embodiment, a design is partitioned, then each partition is verified. In one embodiment, the design is partitioned at the granularity of modules. In another embodiment, the design is partitioned at the granularity of instances. In a third embodiment, instances are grouped together, subject to a weight threshold, so as to form possibly overlapping partitions of instances that are contiguous in the design hierarchy, with the purpose of avoiding, to the extent possible, false negatives. In a further embodiment, the design is partitioned to avoid redundant partitions. In an embodiment, model checking is applied to one or more local properties in each partition. In another embodiment, simulation is used to verify each partition.

Method and system for partitioning an integrated circuit design

Verification systems which employ automata-theoretic formal verification use a model automaton made from a system process (,) representing the system and a task automaton (,) representing the task and use the model automaton to test (,) whether the language of the system process is contained in the language of the task automaton. An improved technique reduces the computational complexity of the language containment testing by producing a model (,) which represents a system which has been automatically localized with regard to a task. Another technique reduces the computational complexity of stepwise refinement (,). In stepwise refinement, the system automaton is refined a step at a time until it reaches the complexity of a practical implementation. The computational complexity of the stepwise refinement is reduced by a technique which permits language containment to be tested using a set of models made from process-automaton pairs rather than process-process pairs.

Automata-theoretic verification of systems

A method wherein a verification tool checks the properties of a system model by performing a partial search of the system-model state space. A partial search is a search wherein the verification tool inputs, at each state of the system-model state space, only a subset or fraction of the complete set of inputs that would have been used during a conventional search. Performing a partial search, instead of a conventional search, reduces the total number of inputs that the verification tool will input to the system model during a search of the system-model state space, thus reducing the amount of computational resources and/or time needed by the verification tool to verify given properties of the system model. Moreover, performing a partial search, instead of a conventional search, does not substantially reduce the ability of the verification tool to identify errors in the system-model.

Verification tool computation reduction

A method and apparatus for efficiently determining whether a set of constraints input to a verification tool are mutually contradictory or overconstraining. A set of constraints are mutually contradictory or overconstraining when they define values for system-model variables and/or inputs that are inconsistent with each other at a given state or group of states of a system-model state machine. It has been found that when a set of constraints assign inconsistent values at a given state or group of states of the system-model state space, the verification tool will treat the given state or group of states as a so-called non-returnable state. That is, the verification tool will not recognize any paths from the given state or group of states to a set of reset states. As a result, instead of having to analyze the values defined by every constraint input to the verification tool, it can be determined whether a set of constraints input to the verification tool are mutually contradictory or overconstraining by analyzing only the constraints enabled at the non-returnable states.

Constraint validity checking

A method and apparatus for verifying the behavior of properties or functions of a system by forming a reduced model for each property of the system, and running a given simulation operation on the reduced model to verify the behavior of each said property. When a property or function does not behave as expected, the system model is adjusted, and only those functions having a property affected by the adjustment are rechecked. In one illustrative embodiment, a system model is reduced by eliminating all variables having no effect on the function or property being checked. The resulting reduced model can be further reduced by adjusting the range of each variable therein to a minimum range necessary to check the behavior of that specific property. If it becomes necessary to change the system model in order to fix a problem relative to one property, then only those properties having a reduced model affected by that change or fix are re-verified.

Efficient regression verification

The invention concerns ascertaining whether the successful accomplishment of a defined task by a simpler model of a complex system implies that the complex system will also accomplish the defined task. The invention performs the ascertainment by checking language containment of the two models.

Verification of homomorphism between two system models

The invention concerns reduction of a complex model of a system to a simpler model. The invention defines a task postulates a simple sub-system, and inquires whether the sub-system achieves the task. If not, the invention selects components from the complex model, based on functional relationship of the components to the task, adds the components to the simpler sub-system, and again inquires whether the sub-system achieves the task. The addition process is repeated until a sub-system is attained which does achieve the task.

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Pataskala, OH, United States of America

Ronald H Hardin