Unisys Corporation

Other

Ronald G Arnold

Gregory Allen Marlan

Mitchell A Bauman

Kelvin S Vartti

David C Johnson

Douglas A Fuller

Gary J Lucas

Kenneth L Engelbrecht

Kenneth E Merryman

Ross M Weber

Gerald G Fagerness

Gerald Gregory Fagerness

Edmund J Matras

A dual-channel memory system and accompanying coherency mechanism is disclosed. The memory includes both a request and a response channel. The memory provides data to a requester such as an instruction processor via the response channel. If this data is provided for update purposes, other read-only copies of the data must be invalidated. This invalidation may occur after the data is provided for update purposes, and is accomplished by issuing one or more invalidation requests via one of the memory request or the response channel. Memory coherency is maintained by preventing a requester from storing any data back to memory until all invalidation activities that may be directly or indirectly associated with that data have been completed.

Data acceleration mechanism for a multiprocessor shared memory system

The present invention relates to a method and apparatus for efficiently managing the I/O design of an integrated circuit. The present invention automatically selects and interconnects a number of I/O cells selected from a design library to form an I/O interface. A user interface is provided for receiving a number of parameters provided by the circuit designer. The parameters preferably provide specific information about a circuit design. A set of circuit design assembly rules are also provided, which define the available I/O cells and the appropriate interconnections of the available I/O cells. A computer program then selects and assembles the I/O cells in accordance with the user provided parameters and the set of circuit design assembly rules.

Spreadsheet driven I/O buffer synthesis process

A control store apparatus having flexibility for reprogramming of microcode. A ROM with predetermined microcode is embedded in a microprocessor. A RAM, into which predetermined microcode may be scanned, is also embedded in the microprocessor. An Address RAM stores addresses of the ROM and RAM which are entry points into the microcode. Selection bits are respectively associated with the addresses stored in the Address RAM for selecting between microcode in the ROM and microcode in the RAM. A remapping circuit provides further flexibility. The remapping circuit includes a storage array into which predetermined ROM addresses and respectively associated RAM address may be scanned. The remapping logic circuit is directly coupled to address generation circuitry in the microprocessor for receiving a first part of the ROM address, and is directly coupled to the storage array. The remapping logic circuit is thereby capable of remapping a ROM address to a RAM address efficiently. A second part of the ROM address, which may be generated later than the first part of the ROM address is routed directly to both the ROM and the RAM.

System for programmably providing modified read signals within a

Method and apparatus for performing microcode paging during instruction execution in an instruction processor. In a preferred embodiment an instruction processor is provided that includes both a microcode ROM and a microcode RAM. The microcode ROM stores the current release of the microcode for the computer system, and the microcode RAM stores microcode patch instructions. During instruction execution, the present invention selects between the output of the microcode ROM and the microcode RAM, depending on whether the instruction requires a patch microcode instruction. If the desired microcode patch instruction is not stored in the microcode RAM, the instruction processor is temporarily interrupted and the desired microcode patch instruction or a group of microcode patch instructions are written, or paged, into the microcode RAM.

Method and apparatus for performing microcode paging during instruction

Disclosed is a system for improved instruction fetch prediction. When a jump instruction is encountered, the preceding instruction is considered in predicting the next instruction to fetch. If the preceding instruction is a skip instruction, the result of evaluating a condition specified by the skip instruction is used in predicting the next instruction to fetch. Prediction designators for skip/jump sequences of instructions are maintained in a jump prediction RAM.

Apparatus and method for processing a jump instruction preceded by a

A building block comprising a monolithic matrix of polymer concrete with a row of rectangular steel tubes embedded in the polymer matrix and totally filled by the polymer matrix, and woven fiberglass sheets embedded in the polymer matrix between the upper surfaces of the tubes and the upper surface of the matrix and between the lower surfaces of the tubes and the lower surface of the matrix.

Growing community of inventors

Apple Valley, MN, United States of America

Ronald G Arnold