Texas Instruments Corporation

Ronald F Cormier

Michael Mueck

Frederick J Highton

Michael Douglas Snedeker

Christopher Paul Lash

A capacitance measurement system precharges first terminals (---) of a plurality of capacitors (--), respectively, of a CDAC (capacitor digital-to-analog converter) () included in a SAR (successive approximation register) converter () to a first voltage (V) and pre-charges a first terminal (-) of a capacitor (C) to a second voltage (GND). The first terminals are coupled to the first terminal of the capacitor to redistribute charges therebetween so as to generate a first voltage on the first terminals and the first terminal of the capacitor, the first voltage being representative of a capacitance of the first capacitor (C). A SAR converter converts the first voltage to a digital representation (DATA) of the capacitor. The capacitance can be a touch screen capacitance.

Capacitive measurement system and method

A system for measuring a capacitor (C) precharges a CDAC () in a SAR converter () to a reference voltage (V) and also precharges a first terminal (-) of the capacitor to another reference voltage (GND). During a measurement phase, the CDAC is coupled between an output and an input of an amplifier () and the capacitor also is coupled to the input of the amplifier, so as to redistribute charge between the capacitor and the CDAC. The amplifier generates an output voltage (V) representing the capacitance being measured. The output voltage is stored in the CDAC. The SAR converter converts the output voltage to a digital value representing the capacitance being measured.

Embedded SAR based active gain capacitance measurement system and method

Capacitance measurement system and method

A capacitance measuring system includes analog-digital circuitry () coupled to row conductors () and column conductors () of a touch screen panel (A) for producing a first digital signal (DATA) representative of cross-coupling capacitances (C). Row drive circuitry () superimposes charge transfers from cross-coupling capacitances of the row conductors to a first column conductor to cause the first digital signal to be a convoluted signal. Calibration circuitry () subtracts base line data from the first digital signal to produce a second digital signal (&#x394;DATA) representing touch-induced capacitance change values (&#x394;C). A deconvolution circuit () deconvolutes the second digital signal to produce a digital output () representing a magnitude map of the touch-induced capacitance change values.

Deconvolution-based capacitive touch detection circuit and method

Embedded sar based active gain capacitance measurement system and method

A CMOS image sensor system includes first and second groups of CMOS sensors each responsive to periodic first and second clock signal edges, the second clock signal edge being out-of-phase with the first clock signal edge. Output signals of the first group of CMOS sensors are coupled to a first group of sampling capacitors, respectively, by a first group of sampling switches. Then output signals of the second group of CMOS sensors are coupled to a second group of sampling capacitors, respectively, by means of a second group of sampling switches. Sampled signals on the second group of sampling capacitors to an input of an ADC, and then sampled signals on the first group of sampling capacitors are coupled to the input of the ADC by means of by multiplexing and sample/hold circuitry. A phase of at least one of the first and second clock signal edges is adjusted in response to calibration information so as to avoid circuit noise from being superimposed on sampled signals coupled to the input of the ADC.

Multiple-bank CMOS image sensor system and method

A switched-capacitor sample/hold circuit includes a switched-capacitor input sampling stage and a sample/hold amplifier circuit including an operational amplifier having first and second inputs coupled to first and second input sampling capacitors, respectively, and first and second feedback capacitors coupled between the first and second inputs and first and second outputs of the operational amplifier. A continuous-time offset DAC receives a digital input signal representative of an offset voltage produces first and second offset correction voltages. The first and second offset correction voltages are coupled to the switched-capacitor sample/hold circuit to adjust the amount of pre-charging of the first and second feedback capacitors, respectively, in accordance with the value of the digital input signal to compensate an offset component associated with the and second input voltages. The output of the switched-capacitor sample/hold circuit can be connected to an ADC.

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Tucson, AZ, United States of America

Ronald F Cormier