International Business Machines Corporation

Ronald Eugene Bodner

Thomas L Crooks

Israel B Magrisso

Keith K Slack

Richard Craig Kiscaden

Richard S Smith

Andrew Henry Wottreng

Mario N Cianciosi

Keith M Slack

John E Guest

Addressing control apparatus is structured to provide either byte or word addressing of storage organized on a word basis. The storage address register is made shiftable whereby for byte operations, it is shifted, and the bit shifted out of the register is used for byte selection. The contents of the storage address register are used to address storage for both word and byte addressing, and no change is required. The storage access, however, for byte addressing takes place after the shift is completed and the timing is adjusted to account for the shift operation. Gate control logic is modified to facilitate the byte selection.

Apparatus for enabling byte or word addressing of storage organized on a

A register control instruction is added in a stored program computer and uses the same OP code as used for an existing storage instruction. A non used bit state in the existing storage instruction identifies the instruction as a register control instruction rather than a storage instruction and causes logic to generate a control signal for inhibiting the storage operation whereby the storage address is used for addressing a register instead of storage and data is transferred to or from the addressed register as per other control information in the instruction. The bit state identifying the instruction as a register control instruction is converted to a used bit state of the storage instruction so as to invoke an address update operation normally invokable by the storage instruction to update the storage address used instead for register addressing.

Instruction processing control apparatus

Storage protection is provided in a computer system having address translation by loading address translate registers with valid translated addresses and with special addresses. A circuit for generating a storage exception signal is connected to receive all addresses from the translate registers which are addressed by the main storage address and generates a storage exception signal in response to detecting a special address. The address translation mode is provided for both a main storage processor and a control processor with a separate address translate control register for each processor. Address translation is automatically selected based upon interrupt level. Address translation registers are also provided for I/O operations and are controlled independently from and can be in parallel with the task address translation registers.

Address translation with storage protection

An asymmetrical multiprocessor system has a main storage or macroprocessor connected under control of a microprocessor for initiation and termination of operation of the macroprocessor. The macroprocessor after being started by the microprocessor runs until a check condition in the macroprocessor occurs, a non-executable operation code (OP code) in the macroprocessor is encountered, or the microprocessor wants control. When the macroprocessor stops the microprocessor is interrupted. The interrupt routine handles the condition causing the interrupt and restarts the macroprocessor. Non-executable OP codes include supervisor call and invalid OP codes. I/O operations are handled by the supervisor call instruction.

Asymmetrical multiprocessor system

Data transfers between input/output (I/O) devices and a central processing unit (CPU) take place under instruction or base cycle steal control a byte at a time where the I/O device attachments connect to ports and the ports connect to the CPU. Data transfer can be synchronous or asynchronous. The port involved in the data transfer sends out a device address and command information simultaneously on port data bus out and command bus out, respectively, to the I/O attachments. The addressed I/O device can respond any time within a predetermined time interval. If an I/O device does not respond within the time interval, a blast condition generated by the port causes the I/O attachments to clear the busses between it and the port. During execution of an I/O instruction, the CPU clock is first held in a particular time state while phase clocks and port clocks continue to run and synchronization between the port and I/O attachment is taking place. Upon completion of the synchronization sequence, the port generates an advance time signal to the CPU to advance the CPU clock. The CPU clock runs and the storage clock can be activated depending upon the type of I/O instruction being executed, the CPU clock runs until it reaches a second particular time state and then remains at that particular time state until the port again generates an advance time signal to the CPU. The activity taking place as the CPU clock is advancing depends upon the type of I/O instruction, but generally a data transfer occurs, and the data is entered into or transferred from local storage registers or main or control storage. The extended second particular time state is used for a de-synchronization sequence between the port and I/O attachment.

I/O data transfer control system

The first time period of the instruction fetch cycle is eliminated when fetching the branch to instruction in a computer system operating in a non-overlap mode. Whenever a branch instruction is decoded, the storage address register (SAR) is directly loaded during execution of the branch instruction with certain bits from a storage data register (SDR) concatenated with certain bits from an operand register to form the branch to address in SAR. The instruction counter is incremented in the usual manner but the incremented address is not loaded into SAR. The clock is advanced to the second rather than the first time state of the next instruction fetch cycle. Thereafter, the branch to address which is residing in the operand register, is incremented and loaded into the instruction counter.

Computer control apparatus

Control circuitry in a computer system is responsive to an allow cycle steal signal from an I/O attachment operating in a burst or dedicated data transfer mode and generates control signals whereby the next data storage cycle is made available to an I/O device which is also capable of operating in a cycle steal mode. Upon completion of the next storage cycle, the operation reverts to burst mode and the I/O attachment operating in the burst mode is granted ensuing data storage cycles until it relinquishes a storage cycle to an I/O device capable of using and having a need for it.

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Rochester, MN, United States of America

Ronald Eugene Bodner