Siemens Gammasonics, Inc.

G.d. Searle & Company

Ronald E McKeighen

Michael P Buchin

A dynamically variable electronic delay line for real time ultrasonic imaging systems is disclosed which controllably phases the signals associated with an array of electromechanical transducer elements and thereby enables selective scanning and dynamic focusing of a target. A controllable variable electronic time delay apparatus is coupled to each of the electromechanical transducer elements of the array having separate write-in and read-out addressing capabilities. The signals associated with a respective ultrasonic transducer element are fed in at selected write-in addresses and subsequently read-out and extracted after an initial time delay interval. The write-in and read-out address pointers of the memory system are continuously sequenced during operation of the device and the time delay interval is a function of the difference between the addresses and the clock rate. The initial delay can be varied instantaneously by modifying either the write-in or the read-out address pointer during the sequencing thereof, such modification being defined as an 'edit-splice' technique. In the preferred embodiments of the invention, the time delay apparatus comprises a trio of analog shift register memories of the change coupled device (CCD) type for each transducer section together with commutating write and read means. Both the write and read means for each CCD trio are independently controllable for use in an 'edit-splice' imaging system.

Permutating analog shift register variable delay system

A dynamically variable electronic delay line for real time ultrasonic imaging systems is disclosed which controllably phases the signals associated with an array of electromechanical transducer elements and thereby enables selective scanning and dynamic focusing of a target. A controllable variable electronic time delay apparatus is coupled to each of the electromechanical transducer elements of the array having separate write-in and read-out addressing capabilities. The signals associated with a respective ultrasonic transducer element are fed in at selected write-in addresses and subsequently read-out and extracted after an initial time delay interval. The write-in and read-out address pointers of the memory system are continuously sequenced during operation of the device and the time delay interval is a function of the difference between the addresses and the clock rate. The initial delay can be varied instantaneously by modifying either the write-in or the read-out address pointer during the sequencing thereof, such modification being defined as an 'edit-splice' technique. In the preferred embodiments of the invention, the time delay apparatus comprises a trio of analog shift register memories of the charge coupled device (CCD) type for each transducer section together with commutating write and read means. Both the write and read means for each CCD trio are independently controllable for use in an 'edit-splice' imaging system.

A dynamically variable electronic delay line for real time ultrasonic imaging systems is disclosed so as to controllably phase the signals associated with an array of electro-mechanical transducer elements and thereby enable the selective scanning and dynamic focusing of a target. A controllable variable electronic time delay apparatus is coupled to each of the electromechanical transducer elements of the array and in one embodiment thereof constitutes an electronic memory having separate write-in and read-out addressing capabilities. The signals associated with a respective ultrasonic transducer element are fed in at selected write-in addresses and subsequently read-out and extracted after an initial time delay interval. The write-in and read-out address pointers of the memory are continuously sequenced during operation of the device and the time delay interval is a function of the difference between the addresses, as well as the clock rate. The initial delay can be varied by instantaneously modifying either the write-in or the read-out address pointer during the sequencing thereof, such modification being defined as an 'edit-splice' technique. In other embodiments of the invention, the time delay apparatus could comprise a multiple cell memory or register in which a plurality of signals from an associated transducer element are stored and subsequently read-out after an initial time delay, which delay can be changed either by varying the effective length of the shift register or by varying the clock rate at which the shift register advances the signals stored therein, or through an 'edit-splice' technique as above-described.

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Hoffman Estates, IL, United States of America

Ronald E McKeighen