Honeywell Information Systems Inc.

Ronald E Lange

Robert J Koegel

Richard J Fisher

Steve E King

Steven H Webber

Riley H Dobberstein

Terry L Davis

Apparatus for entering encoded data, command, and address information via a keyboard for transfer to an automated maintenance system designed to perform certain tests on or cause selected events in a unit of a data processing system such as the central processing unit. The data, command and address information entered via the keyboard by an operator serves to control the tests performed by or the events caused by the automated maintenance system. The maintenance panel also includes a plurality of display devices for displaying the data, command and address information sent to the automated maintenance system as well as data received by the automated maintenance system from the unit under test indicating the correctness of its performance. In the preferred embodiment, several LED indicators are also used for prompting and status indication. Some of these LED's light under the control of the automated maintenance system to provide prompting to the operator to cause him to enter information necessary for completion of a particular command he has entered via the keyboard. Such additional information depends upon the command entered and might include the data he desires to write to a particular register or memory location or the address of a particular memory location he wishes to read. The other LED's indicate the status of the system such as whether an operation is complete or whether the remote terminal port has been enabled. In the preferred embodiment, a hexadecimal encoded keyboard is used for entering data, addresses and commands, while eight function keys serve to control various operations by the automated maintenance system.

Maintenance panel for communicating with an automated maintenance system

An apparatus for conducting input output operations with another data processing device in a flexible and low cost manner is comprised of a programmed microprocessor coupled to a keyboard, a parallel port, and a modem. The microprocessor is programmed to periodically scan the keyboard to determine what keys if any are depressed. It also scans the parallel port for incoming data and senses incoming data from the modem by sensing a start bit. Control characters from the keyboard can set options such that incoming data from an input can be simultaneously sent out from the modem and/or parallel port.

Microprocessor based computer terminal

There is disclosed herein an apparatus for displaying data and communicating with another data processing device via a parallel port or over a long distance communications network via a full duplex modem, said computer terminal utilizing a microprocessor for programmed control of the terminal. The terminal is capable of displaying information on a standard black and white television set and utilizes a keyboard for entering information to be displayed or sent to the main data processing system. Limited graphics with sixty four graphics patterns are also available by using the microprocessor chip to scan the keyboard and communicate with the modem and parallel ports, and by utilizing a standard television set instead of a cathode ray tube, substantial material cost savings can be made in building the terminal which could be built for under $250 in parts in 1979.

Low cost programmable video computer terminal

There is disclosed herein an apparatus for encoding, storing, updating and decoding data indicating the order of usage of memory locations as in a cache memory. An array of memory bits is encoded by a field programmable logic array each time a memory device or other peripheral is accessed by a method which need change only a portion of all the memory bits in a row. Each row corresponds to a group of memory locations or peripherals to be monitored. When the order of usage of a group of monitored locations is to be determined a field programmable logic array decodes the corresponding row and outputs a signal indicating the least recently used one of the memory locations of interest.

Apparatus for recording the order of usage of locations in memory

An apparatus is disclosed herein for providing faster memory access for a CPU by utilizing a least recently used scheme for selecting a storage location in which to store data retrieved from main memory upon a cache miss. A duplicate directory arrangement is also disclosed for selective clearing of the cache in multiprocessor systems where data in a cache becomes obsolete by virtue of a change made to the corresponding data in main memory by another processor. The advantage of higher overall speed for CPU operations is achieved because of the higher hit ratio provided by the disclosed arrangement. In the preferred embodiment, the cache utilizes: a cache store for storing data; primary and duplicate directories for identifying the data stored in the cache; a full/empty array to mark the status of the storage locations; a least recently used array to indicate where incoming data should be stored; and a control means to orchestrate all these elements.

Cache memory utilizing selective clearing and least recently used

There is disclosed herein an apparatus for use in automated testing of elements in data processing systems such as the central processing unit. The system is comprised of a microprocessor with associated firmware, RAM and peripheral communications devices. There are two communication interface ports for receiving commands and instructions from local and remote computer terminals or from data processing units programmed to cause the testing apparatus to perform predetermined sequences of tests. There is also a port for connection to a portable maintenance panel which can be held in the hand of a field engineer for controlling the testing apparatus. The system is designed to replace prior art maintenance panels used for debugging computer hardware.

Microprocessor based maintenance system

Apparatus for use in coupling an automated maintenance system of general utility to a central processing unit of a data processing system. The interface apparatus is comprised of path control and operational condition control registers to control and enable the paths accessed by the automated maintenance system and to control the conditions of operation of the central processing unit. A control point register stores control point information from the central processing unit indicating its internal status. This information is read and displayed by the automated maintenance system. Address and data registers serve to buffer data and addresses exchanged between the automated maintenance system and the CPU. The disclosed interface apparatus allows a general utility automated maintenance system to be adapted to test a specific central processing unit.

Interface circuit for coupling an automated maintenance system to a CPU

In a data processing system that uses segmentation and paging to access data information such as in a virtual memory machine, the cache store need not be entirely cleared each time an I/O operation is performed or each time the data in the cache has a possibility of being incorrect. With segmentation and paging, only a portion of the cache store need be cleared when a new page is obtained from the virtual memory. The entire cache store is cleared only when a new segment is indicated by the instruction. The cache store is selectively cleared of the information from the page whose data information is no longer needed by addressing each level of an associative tag directory to the cache store. The columns of each level are compared to the page address and if a comparison is signaled that column of the addressed level is cleared by clearing the flag indicating the full status of the column in the addressed level. Each level of the tag directory is addressed.

Growing community of inventors

Phoenix, AZ, United States of America

Ronald E Lange