Bull Hn Information Systems, Inc.

Vlsi Technology, Inc.

Koninklijke Philips Corporation N.v.

Other

Honeywell Bull, Inc.

Ronald E Lange

William A Shelly

Russell Wayne Guenthner

Richard L Demers

Clinton B Eckard

Donald C Boothroyd

Leonard Rabins

Wilbur L Stewart

David R Evoy

John E Wilhite

David S Edwards

Ronald W Yoder

Lowell D McCulley

Bruce E Flocken

Peter Chambers

Marion G Porter

Marvin K Webster

David Gerard Spaniol

Jeffrey D Weintraub

A computer system includes a host processor, a first PCI bus, a second PCI bus and a bus bridge. The first PCI bus is coupled with the host processor. The bus bridge interconnects the first and second PCI buses. The bus bridge includes a first portion having a first bridge memory, a second portion having a second bridge memory, and a latency inducing serial bus interconnecting the first portion and the second portion. A method is also taught.

PCI bridge having latency inducing serial bus

A computer system includes a host processor, a first PCI bus, a second PCI bus and a PCI-to-PCI bridge. The first PCI bus is coupled with the host processor. The PCI-to-PCI bridge interconnects the first and second PCI buses. The PCI-to-PCI bridge includes a first portion and a second portion. The first portion includes a first configuration register and the second portion includes a second configuration register. A method is also taught.

PCI bridge configuration having physically separate parts

The present invention comprises a multiple bus master PCI (peripheral component interconnect) bus system within an integrated circuit. The system of the present includes an integrated circuit fabricated onto a single semiconductor die. An internal PCI bus is built into the integrated circuit. The internal PCI bus is adapted to transmit and convey data signals. A plurality of PCI agents are built into the integrated circuit. Each of the plurality of PCI agents are designed to perform a respective function and each of the plurality of PCI agents are coupled to the internal PCI bus to transmit and receive data. The internal PCI bus and the plurality of PCI agents are built into the integrated circuit on the single semiconductor die to create a high performance device.

Multi-master PCI bus system within a single integrated circuit

A method and arrangement for transferring an indeterminate quantity of data from a target data bus to a requesting data bus. A memory block read command is provided to the target bus by an initiating device coupled to an initiating bus. Successive data segments are repeatedly transferred from the target device into a data buffer which is coupled between the initiating and target buses. The data segments are concurrently transferred from the data buffer to the initiating bus while other data segments are being transferred from the target bus into the data buffer. The transfer is terminated upon receipt of the entire desired data block at the initiating bus, and any read-ahead data remaining in the data buffer after this termination is discarded. The concurrent data transfer is allowed when the memory block read command is not in a delayed completion state, and the command response and requested data are next in the response queue.

Selective data read-ahead in bus-to-bus bridge architecture

An arrangement for providing command responses in a sequence that is independent of the sequence that commands are initiated by an initiating bus to a target bus. A first memory array stores commands from the initiating bus in a first sequence, and provides the commands to the target bus in a first sequence. Multiple delayed completion registers are provided, each to receive and store one of the commands entered into the first memory array. The delayed completion registers re-enter its corresponding stored command into the first memory array when a request is received to reissue the command. A second memory array stores command responses in a second sequence that relates to the order that their corresponding commands were successfully completed on the target bus.

Arrangement and method for allowing sequence-independent command

A bridge circuit passes digital information between a primary PCI bus and a secondary PCI bus with increased throughput. The PCI busses carry digital information using respective clock signals having a known minimum skew therebetween. The interface bridge circuit includes primary and secondary PCI bus interfaces configured and arranged to communicate with the primary and secondary PCI busses respectively, and a memory buffer configured and arranged to store the digital information and to be accessed by the primary and secondary PCI bus interfaces. Further, a programmable configuration register is configurable in response to digital configure information received from the primary bus, and is adapted to provide an enable signal to one of the primary PCI bus interface and the secondary PCI bus interface. The enable signal indicates that the digital information is ready in the memory buffer for access by the one of the primary PCI bus interface and the secondary PCI bus interface.

Selective latency reduction in bridge circuit between two busses

An arrangement for transferring information between initiating and target buses, using contiguous command buffering and target bus command decoding. A bus interface bridge circuit includes an initiating bus interface which outputs a plurality of commands, where each of the commands includes a corresponding code. A memory queue is coupled to the initiating bus interface to receive the commands, and to contiguously store the commands into the registers of the queue. A target bus interface is coupled to the output of the memory queue to successively receive the commands. The commands are then executed at targeted devices in accordance with their corresponding codes. A method for transferring commands from an initiating bus to a target bus using contiguous command buffering and target bus command decoding is also provided.

Address/data queuing arrangement and method for providing high data

In order to reduce the size of the memory employed to store firmware, the firmware is written in virtual control words which are then reduced by allotting them to a primary control word memory and at least one secondary control word memory which is addressed by a field in the primary control word memory. A virtual set of secondary control words are each divided into a plurality of fields, and each field of each secondary virtual control word is marked as guarded or 'don't care'. If a field is marked as 'don't care', the function represented by the virtual control word will perform properly no matter what the content of that field. Virtual control word pairs are then examined to ascertain if they can be combined into a single control word. If the guarded fields in the first virtual control word align with the 'don't care' fields in the second virtual control word and vice versa, the two virtual control words can be combined into a single control word containing the contents of the guarded fields from both virtual control words, the remaining fields, if any, remaining 'don't care'. This process may be reiterated to determine if the combined control word can be further combined with another virtual control word. In operation, all the functions represented by a combined control word are executed by calling for that single control word stored in the secondary control word memory.

Method for reducing control store space in a VLSI central processor

In order to efficiently undertake the micro-steps required to execute an extended instruction in a central processing unit, a main sequence controller and a separate basic operations controller having its own sequencer and the ability to run semi-autonomously are provided. Normally, the main sequence controller determines the operation of the basic operations controller, but, in the case of execution of, for example, a multi-word instruction requiring extended basic operations, the basic operations controller temporarily takes control over the main controller until the extended basic operations have been completed. The result is a relatively simple sequencer that supports tight micro-coded functions where many of the sequence decisions can be predetermined.

Basic operations synchronization and local mode controller in a VLSI

Method and apparatus to reduce the number of control words stored in a read only control store of a microprogrammed unit of the CPU of a large scale computer. A set of control fields are required to control the active elements of the unit to cause the unit to execute a large number of different basic operations. Typically the required set of control fields are included in control words stored in a control store controlling the unit during the execution of a basic operation. Obtaining some of the set of required control fields from other sources available within the unit results in a significant reduction in the number of control words stored in the control store without reducing the functionality of the unit.

Method and apparatus for minimizing the number of control words in a

In order to gather, store temporarily and efficiently deliver (if needed) safestore information in a fault tolerant central processing unit having data manipulation circuitry including a plurality of software visible registers, a shadow set of the software visible registers are used in conjunction with shadowing and packing circuitry for copying the contents of the software visible registers, after a data manipulation operation, into the shadow set after the validity of such contents have been verified. In the event of a detected fault in a data manipulation operation, the contents of the shadow set, which will be the last valid set immediately before the error was detected, are transferred back to the software visible registers to institute recovery at the point in the data manipulation immediately prior to that at which the error was detected. Preferably, packing circuitry is included to pack half-word (or shorter) register information into full words in the shadow set to minimize the number of shadow registers and support circuitry required. In the preferred embodiment, during the recovery process, the safestore information in the shadow set is routed through a cache memory which is normally in direct contact with the working register set such that minimum special circuitry is necessary to restore the contents of the working registers. The speed of recovery is enhanced by the use of double word transfers between the shadow set and the software visible working registers via the cache memory.

Automated safestore stack generation and recovery in a fault tolerant

In order to gather, store temporarily and efficiently deliver (if needed) safestore information in a fault tolerant central processing unit having data manipulation circuitry including a plurality of software visible registers, a shadow set of the software visible registers are used in conjunction with shadowing and packing circuitry for copying the contents of the software visible registers, after a data manipulation operation, into the shadow set after the validity of such contents have been verified. In the event of a detected fault in a data manipulation operation, the contents of the shadow set, which will be the last valid set immediately before the error was detected, are transferred back to the software visible registers to institute recovery at the point in the data manipulation immediately prior to that at which the error was detected. Preferably, packing circuitry is included to pack half-word (or shorter) register information into full words in the shadow set to minimize the number of shadow registers and support circuitry required. In the preferred embodiment, during the recovery process, the safestore information in the shadow set is routed through a cache memory which is normally in direct contact with the working register set such that minimum special circuitry is necessary to restore the contents of the working registers.

Automated safestore stack generation and move in a fault tolerant

In order to validate data manipulation results in a CPU which incorporates duplicate BPUs for integrity, which BPUs are typically each implemented on a single VLSI circuit chip, and which is capable of performing single and double precision data manipulation operations, a first BPU transfers to cache storage only the even bits of a given data manipulation result, and a second BPU correspondingly transfers to cache storage only the odd bit information of the result. One BPU segregates the even bits of the result, adds parity information and sends the even bits and parity information to the cache unit. Similarly, the second BPU segregates the odd bits of the result, adds parity information and sends the odd bits and parity information to the cache unit. In the cache unit, the even and odd bit information are separately parity checked before storage into cache memory. If a parity error is observed in either set of information, an error signal is issued to institute appropriate remedial action.

Central processor with duplicate basic processing units employing

In a central processor incorporating at least one co-processor, such as a floating point arithmetic co-processor, in addition to a basic arithmetic logic unit, the problem of rationalizing the contents of the accumulator and supplementary accumulator registers without the burden of speed penalties is addressed and solved. This is achieved by providing input/output access to a common register file and by switching control of the register file to the proper processing unit appropriately. A single, shared accumulator register and a single, shared supplementary accumulator register are included in the stack along with other sharable registers such as address modification registers. Thus, the contents of the accumulator register and the supplementary accumulator register are always up-to-date and available to all processing units in the central processor without the need for first carrying out rationalization steps.

Sharing of register stack by two execution units in a central processor

In order to validate data manipulation results in a CPU which incorporates duplicate basic processing units or integrity, which BPUs are typically each implemented on a single VLSI circuit chip, and which is capable of performing single and double precision data manipulation to obtain first and second data manipulation results, which should be identical, and a cache unit for receiving data manipulation results from both BPUs and for transferring specified information words simultaneously to both BPUs upon request. These operations are controlled by cache interface control signals identically generated in each BPU. In each BPU, the control signals are arranged into first and second groups which are nominally identical. The first control signal group is transmitted to the cache unit from one BPU while the second control group is transmitted to the cache unit from the other BPU. In each BPU, parity is generated for each control group separately. Parity for the group sent to the cache unit by each BPU is included with the control signal information for checking in the cache unit. Parity for the group not sent to the cache unit by each BPU is transmitted to the other BPU and checked against the locally generated parity for that group. In the event of a parity miscompare sensed in either BPU or a parity error sensed in the cache unit, an error signal is issued to institute appropriate remedial action.

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Glendale, AZ, United States of America

Ronald E Lange