International Business Machines Corporation

Ronald DeSales Rossi

Harold Pilo

Steven Harley Lamphier

Roger Andrew Verhelst

Kevin George Petrunich

Nathaniel W Bowe

Paul Stafford Zerr

A method has been found to check contact to chips having inputs lacking a diode to substrate, such as silicon on insulator (SOI) chips. A mid level voltage, such as Vdd/2, is applied to each receiver sequentially to partially turn on both complementary devices of a CMOS inverter receiver or to partially turn on a current switch receiver. The overall chip standby leakage current is measured while a receiver is at the mid level voltage. These measurements are compared to the overall chip standby leakage current in normal operation when a logical high or logical low level is applied to all I/O pads. A mid level voltage is enough to partially turn on both complementary devices of an inverter receiver or to partially turn on a current switch receiver and the current going through that one receiver is sufficient to provide a significant increase in the overall chip standby current. Thus by measuring an overall chip Idd current, probe contact is checked for each receiver pad individually without directly accessing a current at each receiver pad.

CMOS SOI contact integrity test method

Circuit and method are presented for activating/deactivating a special operational mode at power-on of an integrated circuit device having no industry defined test state and/or dedicated test pin. The operational mode is enabled upon powering on the integrated circuit combined with detection of a predefined pattern of a first logic state and a second logic state clocked in successive cycles within a first standard input signal, such as an output enable signal, for a normal operating mode of the device. Special non-functional processing is then performed, such as reading prestored identification data from the integrated circuit and/or testing the integrated circuit via embedded test circuitry including boundary scan or other diagnostic circuitry. This special operational mode is deactivated upon receipt at the integrated circuit device of a second standard input signal, such as a write signal for a random access memory (RAM) device, of a predefined logic state (e.g., write enable state). Deactivating of the special operating mode is transparent to the normal response of the integrated circuit device to the second standard input signal.

Special mode enable transparent to normal mode operation

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Swanton, VT, United States of America

Ronald DeSales Rossi