International Business Machines Corporation

Globalfoundries Inc.

Ronald Dean Goldblatt

Charles Robert Davis

John E Heidenreich, Iii

Sandra Guy Malhotra

John Michael Cotte

Stephen L Buchwalter

Jeffrey Curtis Hedrick

Harold John Hovel

Thomas L McDevitt

Qiang Huang

Xiaoyan Shao

William Francis Landers

Gregory Costrini

Laura Louise Kosbar

Steven Erik Steen

Richard R Thomas

Brett Caroline Baker-O'Neal

Susan Huang

Roland Yudadibrata Utama

Shu-Yun Chong

Rob Steeman

Luis M Ferreiro, Deceased

Domenico Tortorella

Anthony K Stamper

Robert G Biskeborn

Arne Watson Ballantine

Peter Alfred Gruber

Sanjay C Mehta

Kevin Shawn Petrarca

Andrew Herbert Simon

Richard Paul Volant

Thomas M Shaw

George Frederick Walker

Vincent James McGahay

Edward Crandal Cooney, Iii

Stephen Edward Greco

Panayotis Constantinou Andricacos

Raymond R Horton

Tien-Jen Cheng

Nancy Anne Greco

John Gerard Gaudiello

Ronald A Warren

Leena Paivikki Buchwalter

Brett H Engel

Scott W Crowder

Steven E Molis

Caroline A Kovac

Jeffrey D Gilbert

Jae M Park

James Edward Fluegel

Milan Paunovic

Lloyd G Burrell

Glenn Robert Miller

George A Dunbar, Iii

Sharon L Nunes

Frank V Liucci

Diana Llera-Hurlburt

Cheryl Faltermeier

Ned J Chou

David H Yao

Bruce A Root

Photovoltaic devices are formed by laser drilling vias through silicon substrates and, following surface preparation of the via sidewalls, plating a continuous, electrically conductive layer on the via sidewalls to electrically connect the emitter side of the cell with the back side of the cell. The electrically conductive layer can be formed on portions of a base emitter within the vias and on the back side of the substrate. Alternatively, the electrically conductive layer can be formed on a passivation layer on the via sidewalls and back side of the cell.

Method for fabricating a photovoltaic device by uniform plating on dielectric passivated through-wafer vias and interconnects

Method for fabricating a photovoltaic device by uniform plating on emitter-lined through-wafer vias and interconnects

The instant disclosure relates to contact grids for use in photovoltaic cells, wherein a cross-section of the contact grid fingers is shaped as a trapezoid, as well as a method of making photovoltaic cells comprising these contact grids. The contact grids of the instant disclosure are cost effective and, due to their thick metal grids, exhibit minimum resistance. Despite having thick metal grids, the unique shape of the contact grid fingers of the instant disclosure allow the photovoltaic cells in which they are employed to retain more solar energy than traditional solar cells by reflecting incoming solar energy back onto the surface of the solar cell instead of reflecting this energy away from the cell.

Low resistance, low reflection, and low cost contact grids for photovoltaic cells

A device select system according to one embodiment includes an array of first electrical contacts adapted for coupling to a cable; an array of second electrical contacts adapted for coupling to an array of transducers, there being more second electrical contacts than first electrical contacts each of the first electrical contacts being associated with at least two of the second electrical contacts; and a select mechanism for selectively placing each of the first electrical contacts in electrical communication with one of the second electrical contacts associated therewith.

Device select system for multi-device electronic system

A method for sealing an exposed surface of a wire bond pad with a material that is capable of preventing a possible chemical attack during electroless deposition of Ni/Au pad metallurgy is provided. Specifically, the present invention provides a method whereby a TiN/Ti or TiN/Al cap is used as a protective coating covering exposed surfaces of a wire bond pad. The TiN/Ti or TiN/Al cap is not affected by alkaline chemistries used in forming the Ni/Au metallization, yet it provides a sufficient electrical pathway connecting the bond pads to the Ni/Au pad metallization.

Method of fabricating a wire bond pad with Ni/Au metallization

An on-chip redundant crack termination barrier structure, or crackstop, provides a barrier for preventing defects, cracks, delaminations, and moisture/oxidation contaminants from reaching active circuit regions. Conductive materials in the barrier structure design permits wiring the barriers out to contact pads and device pins for coupling a monitor device to the chip for monitoring barrier integrity.

Multi-functional structure for enhanced chip manufacturibility and reliability for low k dielectrics semiconductors and a crackstop integrity screen and monitor

A process is described for forming a common input-output (I/O) site that is suitable for both wire-bond and solder bump flip chip connections, such as controlled-collapse chip connections (C4). The present invention is particularly suited to semiconductor chips that use copper as the interconnection material, in which the soft dielectrics used in manufacturing such chips are susceptible to damage due to bonding forces. The present invention reduces the risk of damage by providing site having a noble metal on the top surface of the pad, while providing a diffusion barrier to maintain the high conductivity of the metal interconnects. Process steps for forming an I/O site within a substrate are reduced by providing a method for selectively depositing metal layers in a feature formed in the substrate. Since the I/O sites of the present invention may be used for either wire-bond or solder bump connections, this provides increased flexibility for chip interconnection options, while also reducing process costs.

Common ball-limiting metallurgy for I/O sites

An electroless touch-up process for repairing copper metallization deposited in dual damascene structures with high aspect ratios. An initial copper strike layer is produced by directional deposition techniques such that discontinuous sidewall coverage occurs. An evolutionary electroless touch-up process then proceeds to conformally grow the copper layer on all surfaces. The result of the evolutionary process is to produce a continuous copper strike layer that can be used with conventional electroplating techniques.

Copper seed layer repair technique using electroless touch-up

A method for increasing the production yield of semiconductor devices having copper metallurgy planarized by a chemical-mechanical planarization process which includes a slurry that contains a conductor passivating agent, like benzotriazole, wherein a non-oxidizing anneal is used to remove any residue which might interfere with mechanical probing of conductive lands on the substrate prior to further metallization steps. The anneal may be performed by any of several techniques including a vacuum chamber, a standard furnace or by rapid thermal annealing.

Method of annealing copper metallurgy

The present invention provides a method for fabricating an integrated circuit (IC) structure having an Al contact in electrical communication with Cu wiring embedded in the initial semiconductor wafer. In accordance with the method of the present invention, the Al contact is formed in areas of the IC structure which contain or do not contain an underlying region of Cu wiring. The present invention also provides a method of interconnecting the fabricated structure to a semiconducting packaging material through the use of a wirebond or Controlled Collapse Chip Connection (C4) solder.

Method/structure for creating aluminum wirebound pad on copper BEOL

Method for treating surface of dielectric polymer with water vapor plasma to form reactive sites and grafting a reactive polymer thereto to tailor the properties of the dielectric polymer surface.

Reactive surface functionalization

A process is disclosed for producing a metal-organic polymer combination by contacting the polymer with a plasma followed by an aqueous solution of a metal salt. In one embodiment a water or nitrous oxide plasma is used to treat a polyimide or a fluorinated polymer. The polymer is combined with a metal cation, the metal being a catalyst for a conventional electroless coating after which it is contacted with an electroless metal plating bath for the formation of electrical circuits and especially for plating high aspect ratio vias in microcircuits. Unlike the conventional electroless process, the cationic catalytic metal is not reduced to a zero valent metal catalyst prior to the application of the electroless metal coating solution. The process also improves the wettability of the polymer, especially the fluorinated polymer and is especially useful in improving the wettability of high aspect ratio vias.

Process for producing a metal organic polymer combination

Method for pressing a material into a through-hole or blind-hole in a substrate. The material is disposed on the surface of the substrate. An environment is provided permitting the material to flow for example by heating the material to the glass transition temperature or above. Thereafter pressure is applied causing the material to flow, first coating the sidewall of the hole and on the continued application of pressure the material flows to completely fill the hole. The resulting substrate can have a substantially planar surface having holes with the periphery coated with or completely filled with the material. The material is preferably a thermoplastic polymeric material such as a polyimide and a perfluorinated polymer.

Lamination method for coating the sidewall or filling a cavity in a

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Yorktown Heights, NY, United States of America

Ronald Dean Goldblatt