Hewlett-packard Company

Hewlett-packard Development Company, L.p.

Adv Antest Corporation

Ronald D Larson

Byron Alan Alcorn

Darel N Emmot

Desi Rhoden

David Pinedo

Roy R Faget

Charles R Dowdell

Thomas L Thrasher

Gil Golov

Larry Jay Thayer

Bryan G Prouty

Monish S Shah

Ulrich Knoch

Thomas Henkel

A method for testing a device-under-test includes receiving, from at least one test channel circuit dedicated to communicate with an input/output pin of the device-under-test by means of at least one hardware resource, at least one logical control command describing a desired operation of the at least one hardware resource, and converting, by means of a resource controller, the at least one logical control command into at least one dedicated control command for the at least one hardware resource, wherein the at least one dedicated control command is adapted to be received by a physical implementation of the at least one hardware resource.

Method and apparatus for testing a device-under-test

A system and method communicate information from a single-threaded application over multiple I/O busses to a computing subsystem for processing. In accordance with one embodiment, a method is provided that partitions state-sequenced information for communication to a computer subsystem, communicates the partitioned information to the subsystem over a plurality of input/output busses, and separately processes the information received over each of the plurality of input/output busses, without first se-sequencing the information.

System and method for communicating information from a single-threaded application over multiple I/O busses

A multi-function unit for occlusion testing primitives being processed in a graphics system and for updating a Z pyramid data structure used for occlusion testing. The Z pyramid data structure is updated on the fly, i.e., as primitives are being occlusion tested. The apparatus comprises multi-function unit is configured to create the Z pyramid data structure and to perform occlusion testing. The Z pyramid data structure comprises a plurality of levels, each of which comprises a plurality of regions. Each region comprises a plurality of subregions, each of which corresponds to a single Z value. Each region corresponds to a plurality of Z values and has a maximum region Z value, which corresponds to the largest Z value of the region. The multi-function unit compares the minimum Z value of each primitive with the maximum Z value of a region associated with the tested primitive to determine whether or not the tested primitive is fully occluded. Coverage masks are maintained by the multi-function unit for the different levels of the Z pyramid data structure to enable the Z pyramid data structure to be updated on the fly. When certain bits in the coverage masks are set, the multi-function unit causes the Z pyramid data structure to be updated.

Multi-function unit of a graphics system for updating a hierarchical Z buffer

In one embodiment, selecting a screen region on a screen of a monitor of a computer graphics display system to activate in rendering a straight line segment. Steps of aligning a rectangular grid to screen region boundaries, wherein the screen includes a screen space divided into at least one screen region, locating a first and second endpoints of the straight line segment on the screen space, defining a rectangular bounding box in the screen space having vertices at the first and second endpoints, identifying each screen region that at least partially overlaps the bounding box, and selecting each identified screen region through which the straight line segment passes to activate for rendering the straight line segment on the screen are disclosed.

Active region determination for line generation in regionalized rasterizer displays

Systems and methods are provided for performing a BLT (BLock Transfer). In accordance with one embodiment, a method uses a texture-mapping subsystem to perform the BLT by configuring the texture-mapping subsystem with coordinate values corresponding to a block of pixels to be transferred. In accordance with another embodiment, an apparatus comprises logic for defining a texture map from a source segment of memory corresponding to a frame buffer, logic for configuring a texture-mapping subsystem with coordinate values corresponding to a first block of pixels on a display, logic for using a texture-mapping subsystem to apply the texture map defined by the configured coordinate values to a destination segment of memory corresponding to a second block of pixels on the graphic display, wherein the application of the texture map effects a BLT of the data from the first block of pixels to the second block of pixels.

System and method for performing BLTs

An apparatus and method of selectively over-sampling image data, anti-aliasing of polygons that produces quality images comparing favorably to full over-sampling techniques while requiring less computation than full over-sampling techniques. Using a hierarchical tiler to perform edge calculations for any given polygon, and then selectively over-sampling pixels along the edge, image quality may be greatly improved through anti-aliasing the polygon edges, with a small increase in computation time or hardware.

Polygon anti-aliasing with any number of samples on an irregular sample grid using a hierarchical tiler

A method and apparatus for performing scan conversion in a computer graphics display system to determine pixel locations in screen space which correspond to a primitive being scan converted. The apparatus of the present invention comprises logic configured to convert a primitive into pixel locations in screen space. The logic, which is referred to hereinafter as the hierarchical tiler, subdivides the screen space into a plurality of regions, each of which comprises a plurality of pixel locations in screen space. The hierarchical tiler then determines whether a particular one of the regions is entirely outside of the primitive, entirely inside of the primitive, or partially inside of the primitive. If the hierarchical tiler determines that a particular region is entirely inside of the primitive, it converts the particular region into pixel locations in screen space. If the hierarchical tiler determines that the particular region is partially inside of the primitive, it further subdivides the particular region into a plurality of sub-regions. The hierarchical tiler then determines whether a particular one of the plurality of sub-regions is entirely outside of the primitive, entirely inside of the primitive, or partially inside of the primitive. If the hierarchical tiler determines that a particular sub-region is entirely inside of the primitive, it converts the particular sub-region into pixel locations in screen space. This process of subdividing the screen space into smaller regions continues until either a region is found to be contained within a primitive and is converted into pixels, or until screen space has been subdivided all of the way down to the pixel level.

Method and apparatus for performing scan conversion in a computer graphics display system

A method and apparatus is provided for performing Z depth comparison tests in a computer graphics display system. The minimum and maximum Z values are calculated for each region of Z values stored in a Z buffer memory device. When a Z value to be tested is received, the Z value is tested against the maximum Z value to determine whether the primitive is occluded. The maximum Z value corresponds to the largest Z value of a region of Z values. The minimum Z value corresponds to the smallest Z value of all of the Z values of the region. If a determination is made that the primitive is not occluded, the received Z value is tested against the minimum Z value. If a determination is made that the received Z value is less than the minimum Z value, the received Z value is retained and is ultimately stored in the Z buffer memory element. The minimum and maximum Z values are updated using the Z values which are contained in the Z buffer memory element. The depth comparison tests may be performed in a frame buffer controller of a computer graphics display system. The controller may comprise a cache memory element for storing a region of Z values and the maximum and minimum Z values associated with the region used in the depth comparison tests. By using the cache memory device in this manner, the number of reads from the Z buffer memory device is reduced.

Method and apparatus for performing Z buffer depth comparison operations

A method and apparatus is provided for interleaving frame buffer controllers in two dimensions. Each frame buffer controller includes an edge stepper, a subspan stepper and a span stepper. The subspan stepper separates each span line into a plurality of parts. Each frame buffer controller provides pixel data for certain parts of the span line. The parts are defined by a start value, a stop value and a starting color value.

System and method for triangle rasterization with frame buffers

Several graphics processing elements are interconnected in a ring using a plurality of individual busses. Each bus interconnects a pair of the graphics processing elements and includes a like group of signal lines for transferring graphics command signals and information signals between graphics processing elements in the ring. Each group of signal lines includes: a group of information signal lines for transferring information between the processing elements; a clock signal line for transferring a clock signal associated with the information signals on the information signal lines to the next processing element in the ring; a ready signal line, on which a ready signal is transferred from a first graphics processing element to a previous graphics processing element in the ring, the ready signal indicating the ability of the first graphics processing element to receive information from the previous graphics processing element; and a group of type signal lines, for transferring type signals indicating the type of operation to be performed on information on the information signal lines. One of the graphics processing elements is a host interface processing element and is coupled to a host processor to receive commands and information signals to be forwarded to the other graphics processing elements in the ring. Each of the graphics processing elements includes: a core processing unit; an interface unit, including a pass through path, which permits command and information signals to be transferred directly through the interface unit to another graphics processing element in the ring, and a backup path, for temporarily storing the forwarded command and information signals; and a plurality of buffers, coupled between the interface unit and the corresponding core processor, for temporarily storing the command and information signals for transfer to the core processing unit.

High speed interconnect bus

An interface circuit included in a ring interconnected group of processing elements includes a backup FIFO to temporarily store information received by the interface circuit when it receives an indication that it temporarily should not forward information to the next processing element in the ring. The interface circuit can receive such an indication, for example, when it receives a signal from the downstream processing element in the ring indicating that the downstream circuit is unable to receive information, or when it receives an information packet requesting a read from the core of the processing element. When the interface circuit receives such an indication, it de-asserts an outgoing ready signal to the upstream processing element in the ring, which should cause the upstream processing element to stop sending information. Once the interface circuit receives an indication that it again may transmit information, the contents of the backup FIFO is released to the output of the interface and possibly is mixed with read data from the core. The control of the flow of information into and out of the backup FIFO is accomplished by storing information in single-bit registers within the control logic of the ASIC in which the interface circuit is implemented that identifies the contents of the various registers in the backup FIFO. In this manner, the information flow into and out of the backup FIFO may be controlled by inspecting the single-bit registers rather than decoding the contents of the backup FIFO itself.

Backup FIFO in-line storage

An interface circuit receives both priority and non-priority information non-concurrently on a shared input bus during a first clock cycle and transmits the information received during the first clock cycle non-concurrently to a shared output bus during a second clock cycle following the first clock cycle. The received information includes status data identifying it as being either priority or non-priority information. All received information is provided to an external circuit via either a priority information path or a non-priority information path, depending on whether the status data included with the information identifies it as being priority or non-priority information. When the interface circuit is unable to transmit information, received information is backed up into either a priority or a non-priority information path, depending on whether the status data included with the information identifies it as being priority or non-priority information. When information is provided from the external circuit to the output of the interface circuit, it may pass though either a priority or a non-priority information path, depending on whether the information identified as being priority or non-priority information.

Dual pipelined interconnect

A computer graphics system utilizes caching of pixel Z values to improve rendering performance. Apparatus for updating the Z values corresponding to pixels of a computer graphics display includes a memory for storing current Z values representing depths at corresponding pixel locations, a Z cache for storing a subset of the current Z values which are stored in the memory, and a comparator for comparing a new Z value with a corresponding current Z value and indicating a pass when the new Z value satisfies a predetermined criteria. The current Z value is read from the Z cache when the current Z value is stored in the Z cache and is read from the memory when the current Z value is not stored in the Z cache. The new Z value is written into the Z cache when the comparator indicates a pass. Each cache entry preferably includes a tile of current Z values corresponding to pixels having a predefined relationship. Different tile configurations may be selected for optimum rendering performance.

Computer graphics system using caching of pixel Z values to improve

Graphics window systems which utilize graphics pipelines and graphics pipeline bypass buses. Hardware solutions for window relative rendering of graphics primitives, block moving of graphics primitives, transfer of large data blocks, and elimination of pipeline flushing are disclosed. The hardware implementations provided in accordance with the invention are interfaced along the pipeline bypass bus, thereby eliminating gross overhead processor time for the graphics pipeline and reducing pipeline latency. Methods and apparatus provided in accordance with the invention exhibit significant pipeline efficiency and reductions in time to render graphics primitives to the screen system.

Growing community of inventors

Fort Collins, CO, United States of America

Ronald D Larson