International Business Machines Corporation

Ronald D Gillingham

James David Strom

Charles Luther Johnson

James Francis Mikos

Kenneth A Bushaw

John T Trnka

Gary W Jorgenson

Clyde L Manning

Michael A Steffes

A digital computer is provided having a clock generation circuit for generating a clock signal in response to an input signal from a fixed-frequency oscillator, which includes a first fixed-frequency oscillator and a second fixed-frequency oscillator, each providing an output signal. Also included is failure detection circuit for detecting a failure of either of the fixed-frequency oscillators, wherein a failure occurs when the first fixed-frequency oscillator or the second fixed-frequency oscillator ceases generating an output. A circuit synchronizing the output from the oscillators is coupled to both the first fixed-frequency oscillator and to the second fixed-frequency oscillator. This synchronizing circuit modifies the output from the second fixed-frequency oscillator to produce a synchronized output that is substantially synchronous with the output from the first fixed frequency oscillator. A switching circuit is coupled to the failure detection circuit, the output from the first fixed-frequency oscillator and the synchronized output of the second fixed-frequently oscillator. The switching circuit normally couples the output of the first fixed-frequency oscillator as the clock signal and wherein in response to a detection of a failure of the first fixed-frequency oscillator, the synchronized output is provided as the clock signal.

Method and apparatus for providing an uninterrupted clock signal in a

A digital system generates a single-phase master clock and distributes it to multiple cards and chips incorporating the functional logic of the system. A circuit in each chip divides the single clock into four spaced clock phases at the same frequency as the master clock. The individual phases are then distributed to functional logic circuits within the same chip. The circuit generates the phases by detecting the midpoints of a triangular wave produced from the single-phase master clock.

Data processing system having four phase clocks generated separately on

A linear image sensor and the video channel associated with the sensor are calibrated to maximize the video signal available. The sensor is limited in output by saturation of the CCD analog shift registers in the sensor. The channel is limited by the range of the analog-to-digital converter in the channel. The useable video signal is maximized by calibrating the sensor relative to its saturation condition and by adjusting the gain of the video channel relative to the range of the analog-to-digital converter. The sensor is calibrated by adjusting its exposure to illumination. The adjustment may be made by adjusting the illumination source or by changing the sampling interval for the sensor. The gain is adjusted by using a variable gain amplifier. A microprocessor monitors the digitized video signal and controls the exposure and gain to calibrate the sensor and channel.

Method and apparatus for calibrating a linear array scanning system

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Rochester, MN, United States of America

Ronald D Gillingham