Advanced Micro Devices Corporation

Ronald C Laugesen

Padmanabha I Venkitakrishnan

Gururaj Singh

Subramanian Narasimhan

P Venkitakrishnan

For each channel, a pair of buffers permits 'non-slip' transfer of data signals on and off a bus synchronized with signals on a time-division multiplexed pulse-code modulation (PCM) highway. A source buffer consisting of a serial-in, parallel-out register and two parallel-in, parallel-out registers receives signals from one of the PCM channels and transmits these signals onto a bus synchronized with a data-routing multiplexer employed within a digital exchange controller employing the device. A destination buffer consisting of two parallel-in, parallel-out registers and a parallel-in, serial-out register receives signal from the bus and, in conjunction with a transmit multiplexer, generates the signals on the PCM highway.

Time-slot assigner multiplexer

An all-digital signal processor (DSP) is disclosed which performs pulse code modulation (PCM) coding and decoding (CODEC) filter operations for both received and transmitted signals, among other functions. A user can access various programmable registers via the microprocessor to specify parameters used in the execution of programs by the DSP. Two 19-bit wide bidirectional data busses are provided for time-division multiplexed communication between various elements, which include a random access memory (RAM), an arithmetic-logic unit (ALU), and an interface to a receive-side analog-to-digital (A/D) converter and a transmit-side digital-to-analog (D/A) converter. A programmed logic array (PLA) executes microcode which controls the processing of signals by the ALU section. A variety of other operations can be performed under control of the PLA such as generation of dual-tone multi-frequency (DTMF) signals commonly used in telecommunications. The architecture of the DSP provides a number of user-accessible registers for the storage of parameters and coefficients used in the generation of the DTMF signals, in the CODEC filtering, and in the compression and expansion of signals. The design of the general-purpose DSP is readily expandible to accomodate additional circuit elements and/or more signals to be processed in parallel.

Streamlined digital signal processor

A monolithic integrated circuit chip preferably includes a pair of data busses capable of conducting in parallel the number of signals which can be processed simultaneously by the components on the chip. Signals on the busses are carried in a time-multiplexed manner, each bus having a predetermined number of time slots. Preferably, each component on the chip is connected to one or both of the busses and is assigned a particular time slot for the bus to which it is connected. The resulting chip is of a structured, rather than a custom, design. Accordingly, it can be readily expanded or contracted in the number of signals which can be simultaneously processed. The number of components which can be included on the chip is limited only by the number of time slots available on the bus to which it is connected. By providing two busses, such common circuit elements as two-input adder/subtractors can be readily accommodated by a chip designed according to the instant invention. The bit-slice organization of the chip significantly reduces the design effort of the components connected to a bus, since a one-bit slice is merely replicated for each conductor of the bus. Ease of expansion along this dimension is achieved at virtually no cost.

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Los Gatos, CA, United States of America

Ronald C Laugesen