International Business Machines Corporation

Ronald A Sasaki

Edward Butler

Endre P Thoma

Robert Tamlyn

A frame buffer construction and data storage technique for computer graphics display systems are presented employing a plurality of on-chip color registers. The plurality of on-chip color registers facilitate block writing and flash writing of multiple color information into the main frame buffer video memory. Addressing of the plurality of color registers is achieved at a column address strobe (CAS) cycle page mode rate for both the loading of the registers and the block or flash writing of the contents of the registers into the main memory array.

Multiple data registers and addressing technique therefore for

A multimedia dynamic random-access memory (DRAM) or video random-access memory (VRAM) having enhanced block overwrite capabilities includes a plurality of sense amplifiers which are selectively coupled to an array of memory cells via paired bit lines for sensing/writing charge to the memory cells. Each sense amplifier is controlled by a primary set device and a secondary set device. The secondary set device is of smaller size than the primary set device but still sized sufficiently to maintain accessed data appearing on the paired bit lines. Upon decoding of a block overwrite request, the primary set device is momentarily turned off to facilitate forcible overwriting of selected sense amplifiers with new data while the secondary set device maintains data appearing on unselected sense amplifiers. Once block overwrite is complete, the primary set device is reactivated and charge is restored to the memory cells. By momentarily deactivating the primary set device, block overwriting of a large number of bit line pairs is possible.

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San Jose, CA, United States of America

Ronald A Sasaki