International Business Machines Corporation

Globalfoundries Inc.

Ronald A Piro

Albert Manhee Chu

Rohit Pradeep Shetty

Douglas Wayne Kemerer

Daryl Michael Seitzer

Thomas W Wyckoff

Guy R Richardson

Elliot L Gould

Lance A McAllister

Deborah A Wellburn

Michael Richard Ouellette

George Maria Braceras

Kevin William Gorman

Douglas Willard Stout

John S Austin

Steven Michael Eustis

Peter Francis Croce

Allen R Carl

A read only memory (ROM) with redundancy and methods of use are provided. The ROM with redundancy includes a programmable array coupled to a repair circuit having one or more redundant repairs. The one or more redundant repairs include a word address match logic block, a data I/O address, and a tri-state buffer. The word address match logic block is provided to the tri-state buffer as a control input and the data I/O address is provided to the tri-state buffer as an input. An output of the tri-state buffer of each redundant repair is provided as a first input to one or more logic devices. One or more data outputs of a ROM bit cell array is provided as a second input to a respective one of the one or more logic devices.

Read only memory (ROM) with redundancy

A semiconductor device structure is embedded within a semiconductor chip that calibrates a photon-emission luminosity scale by running multiple known currents through the device. The method comprises embedding at least one photon emission device in an integrated circuit having at least one functional device. A control current is applied to the at least one photon emission device. The photon emission intensity produced by the at least one photon emission device is captured. The current density of the at least one photon emission device is calculated. A test current is applied to the at least one functional device. The photon emission intensity produced by the at least one functional device is captured. The current density of the at least one functional device is estimated based on a comparison with the calculated current density of the at least one photon emission device.

Embedded photon emission calibration (EPEC)

A method and structure for a pair of read only memory (ROM) cells having a first latch and a second latch connected to the first latch. The first latch and the second latch behave as master and slave latches to one another. The first latch and the second latch include a write bitline connection that is permanently connected to a fixed voltage source to permanently program the first latch and the second latch to permanent ROM values.

Compilable writeable read only memory (ROM) built with register arrays

Disclosed is a novel circuit technique that will significantly improve the noise margin of a passgate latch design. The circuit technique consists of a passgate latch with additional circuitry for sensing the occurrence of coupled noise and then turning on a current mirror that injects current into the latch internal node to stabilize the latch. The circuit further includes a disabling system for disabling the additional circuitry during normal operation of the passgate latch.

Couple noise protection circuit technique

An output driver circuit for a semiconductor chip has a push-pull output with a P-channel pull-up and an N-channel pull-down. Predrivers produce push-pull outputs for driving the gates of the output driver. Compensator circuits, one for the N-channel pull-down, and one for the P-channel pull-up, are used to prevent the transition from high-to-low or low-to-high from being too rapid, which could cause noise due to inductance of the package leads. A feedback circuit halts the operation of the compensator circuits after a short interval. An overvoltage circuit formed in a well of the semiconductor chip holding the driver circuit, having an input coupled to receive the data output of the predriver circuit going to the P-channel pull-up, also functions to prevent damage to the output driver circuit due to overvoltage on the output node. A stack of diodes connected in a forward direction between the N-well of the P-channel pull-up transistor and the positive terminal of the voltage supply serves to clamp the output node if it tends to go above a selected overvoltge level.

Low-power, tristate, off-chip driver circuit

A method and semiconductor structure are provided for intermixing circuits of two or more different cell classes, such as standard cells and gate array cells, on a common chip or substrate with minimum gound rule separation between adjacent cells of different classes. Cell locations are defined with given boundaries and contiguously arranged on the surface of a semiconductor chip, and then either standard cell type or gate array type circuits are formed within any of the cell locations to provide a structure for balancing chip density and performance versus hardware turn-around-time.

Method of combining gate array and standard cell circuits on a common

A CMOS off-chip driver circuit is provided which includes a P-channel pull up transistor and an N-channel pull down transistor serially arranged between a first voltage source having a supply voltage of a given magnitude and ground with the common point between the transistors forming an output terminal to which is connected a circuit including a second voltage source having a supply voltage of a magnitude significantly greater than that of the given magnitude. A first P-channel field effect transistor is connected between the output terminal and the gate electrode of the pull up transistor. A first input terminal is coupled to the gate electrode of the pull up transistor through a transmission gate including a first N-channel field effect transistor arranged in parallel with a second P-channel field effect transistor, with a gate electrode of the first N-channel transistor being connected to the first voltage source and the gate electrode of the second P-channel transistor being connected to the output terminal.

CMOS off chip driver circuit

A method and semiconductor structure are provided for intermixing circuits of two or more different cell classes, such as standard cells and gate array cells, on a common chip or substrate with minimum ground rule separation between adjacent cells of different classes. Cell locations are defined with given boundaries and contiguosuly arranged on the surface of a semiconductor chip, and then either standard cell type or gate array type circuits are formed within any of the cell locations to provide a structure for balancing the chips density and performance versus hardware turn-around-time.

A substrate bias generator or circuit is provided which includes a charge pump having a series circuit with first and second nodes connected between a semiconductor substrate and a point of reference potential. A first voltage having a first phase is coupled to the first node and a second voltage having a second phase is coupled to the second node. A field effect transistor is connected between the substrate and the second node and the control electrode of the transistor is connected to the first node. The series circuit includes first and second devices, preferably diodes, with the first device being connected between the first node and the point of reference potential and the second device being connected between the first and second nodes.

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Essex Junction, VT, United States of America

Ronald A Piro