Intel Corporation

Ronak Singhal

Bret L Toll

Glenn J Hinton

Buford M Guy

Mishali Naik

Per H Hammarlund

Sreenivas Subramoney

Avinash Sodani

Lihu Rappoport

Robert S Chappell

Sebastien Hily

David M Durham

Gilbert A Neiger

Hong Wang

Andrew V Anderson

Richard A Uhlig

Ravishankar Iyer

Stephan Jourdan

Andrew J Herdrich

Darrell D Boggs

Deborah T Marr

Sailesh Kottapalli

Edwin Verplanke

Julius Yuli Mandelblat

Jeffrey D Chamberlain

John G Holm

Xiangbin Wu

Christopher C Gianos

Steven E Raasch

Elmoustapha Ould-Ahmed-Vall

Christopher J Hughes

Jesus Corbal

Jason W Brandt

Edward Thomas Grochowski

Francis X Mckeen

Stephen H Gunther

David J Sager

David B Papworth

Stanislav Shwartsman

Douglas M Carmean

Jayesh Gaur

Adrian C Moga

Thomas R Huff

James D Allen

Niranjan K Soundararajan

Seyed Yahya Sotoudeh

Pooja Roy

Zeev Sperber

Shubhendu Sekhar Mukherjee

Raanan Sade

Matthew C Merten

Michael A Fetterman

Saurabh Gupta

Eric A Sprangle

Adi Yoaz

Anant V Nori

Jared Warner Stark, Iv

Rahul Pal

Arijit Biswas

Anwar Q Rohillah

Hermann Gartler

John Alan Miller

Kenneth J Janik

Laura A Knauth

Ryan Carlson

Ragavendra Natarajan

Omar M Shaikh

Liron Zur

K S Venkatraman

Yiftach Gilad

Hanna Alam

Prathmesh Kallurkar

Michael Fetterman

Christopher J Shannon

Alexandr Titov

Daniel Deng

Hugh M Caffey

Niranjan Kumar Soundararajan

Methods and apparatus relating to de-prioritizing speculative code lines in on-chip caches are described. In an embodiment, logic circuitry determines whether a storage structure includes a reference to a code miss request prior to transmission of the code miss request to a shared cache. The logic circuitry causes de-prioritization of a code line, corresponding to the code miss request, in the shared cache in response to an absence of the reference in the storage structure. Other embodiments are also disclosed and claimed.

De-prioritizing speculative code lines in on-chip caches

Systems, methods, and apparatuses for resource bandwidth monitoring and control are described. For example, in some embodiments, an apparatus comprising a requestor device to send a credit based request, a receiver device to receive and consume the credit based request, and a delay element in a return path between the requestor and receiver devices, the delay element to delay a credit based response from the receiver to the requestor are detailed.

Systems, apparatuses, and methods for resource bandwidth enforcement

Embodiments of an invention a processor architecture are disclosed. In an embodiment, a processor includes a decoder, an execution unit, a coherent cache, and an interconnect. The decoder is to decode an instruction to zero a cache line. The execution unit is to issue a write command to initiate a cache line sized write of zeros. The coherent cache is to receive the write command, to determine whether there is a hit in the coherent cache and whether a cache coherency protocol state of the hit cache line is a modified state or an exclusive state, to configure a cache line to indicate all zeros, and to issue the write command toward the interconnect. The interconnect is to, responsive to receipt of the write command, issue a snoop to each of a plurality of other coherent caches for which it must be determined if there is a hit.

Apparatuses and methods for a processor architecture

A processor includes a first mode where the processor is not to use packed data operation masking, and a second mode where the processor is to use packed data operation masking. A decode unit to decode an unmasked packed data instruction for a given packed data operation in the first mode, and to decode a masked packed data instruction for a masked version of the given packed data operation in the second mode. The instructions have a same instruction length. The masked instruction has bit(s) to specify a mask. Execution unit(s) are coupled with the decode unit. The execution unit(s), in response to the decode unit decoding the unmasked instruction in the first mode, to perform the given packed data operation. The execution unit(s), in response to the decode unit decoding the masked instruction in the second mode, to perform the masked version of the given packed data operation.

Packed data element predication processors, methods, systems, and instructions

Embodiments of an invention for monitoring the operation of a processor are disclosed. In one embodiment, a system includes a processor and a hardware agent external to the processor. The processor includes virtualization logic to provide for the processor to operate in a root mode and in a non-root mode. The hardware agent is to verify operation of the processor in the non-root mode based on tracing information to be collected by a software agent to be executed by the processor in the root mode.

Monitoring the operation of a processor

A processor including an execution unit, an instruction scheduler circuit to identify a first instruction of an instruction stream, identify a second instruction on which execution of the first instruction depends, and assign a first dispatch priority value to the first instruction and the second instruction, and a dispatch circuit to dispatch, based on the first dispatch priority value, the first instruction and the second instruction to an instruction execution circuit.

Criticality based port scheduling

Embodiments of apparatuses, methods, and systems for misprediction-triggered local history-based branch prediction are described. In one embodiments, an apparatus includes a current pattern table and a local pattern table. The current pattern table has a plurality of entries, each entry in which to store a plurality of pattern lengths of a current pattern of one of a plurality of branch instructions. The local pattern table is to provide a first branch prediction based on the current pattern.

Misprediction-triggered local history-based branch prediction

A processor includes a memory to hold a buffer to store data dependencies comprising nodes and edges for each of a plurality of micro-operations. The nodes include a first node for dispatch, a second node for execution, and a third node for commit. A detector circuit is to queue, in the buffer, the nodes of a micro-operation; add, to determine a node weight for each of the nodes of the micro-operation, an edge weight to a previous node weight of a connected micro-operation that yields a maximum node weight for the node, wherein the node weight comprises a number of execution cycles of an OOO pipeline of the processor and the edge weight comprises a number of execution cycles to execute the connected micro-operation; and identify, as a critical path, a path through the data dependencies that yields the maximum node weight for the micro-operation.

Efficient hardware-based extraction of program instructions for critical paths

A processor of an aspect includes a set of registers capable of storing packed data. An execution unit is coupled with the set of registers. The execution unit is to access the set of registers in at least two different ways in response to instructions. The at least two different ways include a first way in which the set of registers are to represent a plurality of N-bit registers. The at least two different ways also include a second way in which the set of registers are to represent a single register of at least 2N-bits. In one aspect, the at least 2N-bits is to be at least 256-bits.

Processors, methods, and systems to access a set of registers as either a plurality of smaller registers or a combined larger register

A processor includes N-bit registers and a decode unit to receive a multiple register memory access instruction. The multiple register memory access instruction is to indicate a memory location and a register. The processor includes a memory access unit coupled with the decode unit and with the N-bit registers. The memory access unit is to perform a multiple register memory access operation in response to the multiple register memory access instruction. The operation is to involve N-bit data, in each of the N-bit registers comprising the indicated register. The operation is also to involve different corresponding N-bit portions of an M&#xd7;N-bit line of memory corresponding to the indicated memory location. A total number of bits of the N-bit data in the N-bit registers to be involved in the multiple register memory access operation is to amount to at least half of the M&#xd7;N-bits of the line of memory.

Multiple register memory access instructions, processors, methods, and systems

Growing community of inventors

Portland, OR, United States of America

Ronak Singhal