Foundry Networks, Inc.

Ati International Srl

Ronak Patel

Andrew Zhenwen Chang

Ming G Wong

Yu-Mei Lin

Yuen Fai Wong

Ming Fung Wong

Korbin S Van Dyke

Ian Edward Davis

Paul W Campbell

Niteen Aravind Patkar

Shalesh Thusoo

Sanjay Mansingh

T R Ramesh

Gurjeet Singh Saund

Tr Ramesh

Jeffrey A Prince

Greg L Ries

A backplane interface adapter with error control and redundant fabric for a high-performance network switch. The error control may be provided by an administrative module that includes a level monitor, a stripe synchronization error detector, a flow controller, and a control character presence tracker. The redundant fabric transceiver of the backplane interface adapter improves the adapter's ability to properly and consistently receive narrow input cells carrying packets of data and output wide striped cells to a switching fabric.

Backplane interface adapter with error control and redundant fabric

A backplane interface adapter for a network switch. The backplane interface adapter includes at least one receiver that receives input cells carrying packets of data; at least one cell generator that generates encoded cells which include the packets of data from the input cells; and at least one transmitter that transmits the generated cells to a switching fabric. The cell includes a destination slot identifier that identifies a slot of the switching fabric towards which the respective input cell is being sent. The generated cells include in-band control information.

Backplane interface adapter

According to an embodiment of the invention, a network device such as a router or switch provides efficient data packet handling capability. The network device includes one or more input ports for receiving data packets to be routed, as well as one or more output ports for transmitting data packets. The network device includes an integrated port controller integrated circuit for routing packets. The integrated circuit includes an interface circuit, a received packets circuit, a buffer manager circuit for receiving data packets from the received packets circuit and transmitting data packets in one or more buffers and reading data packets from the one or more buffers. The integrated circuit also includes a rate shaper counter for storing credit for a traffic class, so that the integrated circuit can support input and/or output rate shaping. The integrated circuit may be associated with an IRAM, a CAM, a parameter memory configured to hold routing and/or switching parameters, which may be implemented as a PRAM, and an aging RAM, which stores aging information. The aging information may be used by a CPU coupled to the integrated circuit via a system interface circuit to remove entries from the CAM and/or the PRAM when an age count exceeds an age limit threshold for the entries.

Network routing system for enhanced efficiency and monitoring capability

A backplane interface adapter with error control and redundant fabric for a high-performance network switch. The error control may be provided by an administrative module that includes a level monitor, a stripe synchronization error detector, a flow controller, and a control character presence tracker. The redundant fabric transceiver of the backplane interface adapter improves the adapter's ability to properly and consistently receive receive narrow input cells carrying packets of data and output wide striped cells to a switching fabric.

A switching fabric having cross points that process multiple stripes of serial data. Each cross point includes a plurality of port slices and ports. Each port includes a plurality of FIFOs, a FIFO read arbitrator, a multiplexer, a dispatcher, and an accumulator. In one embodiment, each cross point has eight ports and eight port slices. A method for processing a stripe of data at a cross point at one port slice includes storing data received from other port slices in a plurality of FIFOs and arbitrating the reading of the stored data. A step of writing data received from a port at the one port slice to an appropriate FIFO in a different port slice is also included. In one embodiment, a method for processing data in port slice based on wide cell encoding and an external flow control command is provided.

Network switch cross point

A backplane interface adapter for a high-performance network switch. The backplane interface adapter receives narrow input cells carrying packets of data and outputs wide striped cells to a switching fabric. One traffic processing path through the backplane interface adapter includes deserializer receivers, a traffic sorter, wide cell generators, stripe send queues, a backplane transmit arbitrator, and serializer transmitters. Another traffic processing path through the backplane interface adapter includes deserialize receivers, a stripe interface, stripe receive synchronization queues, a controller, wide/narrow cell translator, destination queues, and serializer transmitters. An encoding scheme for packets of data carried in wide striped cells is provided.

A computer. When an instruction calling for an architecturally-visible side-effect in an architecturally-visible storage location is recognized, a value is stored representative of an architecturally-visible representation of the side-effect, a format of the representative value being different than an architecturally-visible representation of the side-effect. Execution is resumed without generating the architecturally-visible side-effect. Later, the architecturally-visible representation corresponding to the representative value is written into the architecturally-visible storage location. On a context switch, a context of a first process is written and a context of a second process is loaded to place the second process into execution. At least some instructions maintain results in storage resources outside the context resource set, and instructions are marked to indicate whether or not a context switch may be performed at a boundary of the marked instruction. Instruction execution is monitored for a condition that is a superset of a condition whose occurrence is desired to be detected, and a first exception is raised as a result of recognizing the superset condition. Software filters the superset condition to determine whether the monitored condition has occurred, and if so, the software establishes a second exception to be raised after execution of further instructions of the instruction stream. When it is recognized that an instruction is to affect the execution of a second instruction, the processor is set into single-step mode. After the second instruction is executed, the computer is set out of single-step mode.

Managing instruction side-effects

The present invention provides a high-performance network switch. A digital switch has a plurality of blades coupled to a switching fabric via serial pipes. Serial link technology is used in the switching fabric. Each blade outputs serial data streams with in-band control information in multiple stripes to the switching fabric. The switching fabric includes a plurality of cross points corresponding to the multiple stripes. In one embodiment five stripes and five cross points are used. Each blade has a backplane interface adapter (BIA). One or more integrated bus translators (IBTs) and/or source packet processors are coupled to a BIA. An encoding scheme for packets of data carried in wide striped cells is provided.

High-performance network switch

A system and method for encoding wide striped cells that carry packets of data across stripes. The method encodes an initial block of a first wide striped cell is encoded with initial cell encoding information, and distributes initial bytes of packet data into available space in the initial block of the first wide striped cell. The initial cell encoding information includes control information and state information. One initial block of the first wide striped cell comprises five subblocks corresponding to five stripes. Each subblock includes identical control information and identical state information. The method further includes adding reserve information to available bytes at the end of the initial block of the first wide striped cell. Remaining bytes of packet data are distributed across one or more blocks in the first wide striped cell until an end of packet condition is reached or a maximum cell size is reached. Other steps include encoding the first wide striped cell or another wide striped cell with end of packet information. The end of packet information varies depending upon a set of end of packet conditions, such as, whether the end of packet occurs at the end of an initial block, at the end of the initial block, within a subsequent block, at a block boundary, or at a cell boundary.

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Santa Clara, CA, United States of America

Ronak Patel