Intel Corporation

Ron Zinger

Luke E Girard

A hardware implementation for quotient prediction overrule in high speed higher radix SRT division computation circuits. A quotient prediction PLA receives a data segment of the divisor, together with data values from one or more multiplexors. One multiplexor receives as input a partial remainder from a carry-propagate-adder (CPA), which CPA combines into nonredundant form redundant sum and carry vectors derived from a carry-save-adder (CSA) which determines the next partial remainder. The PLA evaluates the next most significant bits (MSBs) of the divisor together with the next MSBs of the next (unlatched) partial remainder to determine the next quotient bits. The quotient estimates given by the quotient prediction PLA are then transmitted to both quotient and remainder generation logic, including a divisior multiple gating multiplexor. The quotient estimate signals together with a sign signal determine the divisor multiple to be used in the next division iteration during the next clock cycle. When ordinary quotient prediction is to be overridden, the state machine sends an appropriate control signal one clock cycle early, whereafter a divisor multiple of zero is combined with the current partial remainder. A divisor multiple of zero causes a previously derived remainder to be recycled unchanged in the remainder datapath, thereby permitting multicomponent data values (i.e., quotient and remainder) to be sequentially routed along a shared datapath and single output bus. Other non zero divisor multiples can be used to force particular mathematical operations at chosen times. By determining the next quotient bits and the divisor multiple in the current clock cycle the divisor multiple before the the speedpath of the SRT division implementation is substantially improved.

Method and apparatus for overriding quotient prediction in floating

A three-to-two adder which takes advantage of the fact that one of the inputs lags behind the other two inputs. A gate delay is eliminated in the currently preferred embodiment, an output is provided within two gate delays from the time that the last to arrive signal is valid. The adder is implemented using fewer gates than prior art adders.

Three-to-two carry save adder cell

A single, double and extended precision shifter circuit for a hardware floating point divide circuit is disclosed. The divide circuit implements the divide function by receiving two floating point numbers (X and Y) from a main processor, generating the quotient of X/Y using radix 4 SRT nonrestoring division steps, and then delivering the quotient to the main processor. The divide circuit is comprised of a control circuit, a quotient prediction circuit, a partial remainder generator circuit and a quotient generator circuit. The precision shifter circuit operates during the nonrestoring division steps to steer the next negative and positive quotient values generated by the quotient prediction circuit into the proper place within respective negative and positive quotient registers of the quotient generation circuit. The steering is performed according to the precision specified for the divide operation.

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Ron Zinger