Bull Hn Information Systems, Inc.

Ron Yoder

William A Shelly

Russell Wayne Guenthner

Charles P Ryan

Boubaker Shaiek

Eric Earl Conway

Claude Rabel

A processor ( ) contains a Trace RAM ( ) for tracing internal processor signals and operands. A first trace mode separately traces microcode instruction execution and cache controller execution. Selectable groups of signals are traced from both the cache controller ( ) and the arithmetic (AX) processor ( ). A second trace mode selectively traces full operand words that result from microcode instruction ( ). Each microcode instruction word ( ) has a trace enable bit ( ) that when enabled causes the results of that microcode instruction ( ) to be recorded in the Trace RAM ( ).

Data processing system processor dynamic selection of internal signal tracing

A processor ( ) in a data processing system simultaneously loads multiple registers ( ) with a single value for fast domain switching. A domain switch instruction asserts a register block write signal ( ) along with the register write signal ( ) when block writing the single value to the set of registers ( ). Register address lines ( ) are decoded in two sets: a first set of decoded address lines ( ) specifying a block of registers; and the second set ( ) specifying one register in the block of registers. When the register block write signal ( ) is asserted during a register write, the second set of decoded address lines ( ) are ignored, and all registers in the block of registers ( ) selected by the first set of decoded address lines ( ) are simultaneously loaded with a common value. Additional drive requirements are solved either by adding a buffer ( ) to each register bit, or by disabling ( ) the feedback path ( ) in each register bit during block writes.

Data processing system utilizing multiple resister loading for fast domain switching

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Mesa, AZ, United States of America

Ron Yoder