Intel Corporation

Ron Shalev

Raanan Sade

Shlomo Raikin

Stanislav Shwartsman

Robert Valentine

Edward Thomas Grochowski

Michael E Kounavis

Igor Yanover

Julius Yuli Mandelblat

Larisa Novakovsky

Sebastien Hily

Yiftach Gilad

Melih Ozgul

Ephi Zehavi

Boris Ginsburg

Zhao Xudong

In one embodiment, a heterogeneous multicore processor is described that is optimized to execute multi-stage computer vision algorithms such as cascade classifier workloads. In such embodiment the heterogeneous processor includes at least one SIMD core, such as a vector processor core, coupled with one or more scalar cores. In one embodiment the heterogeneous multiprocessor executes multi-stage compute operations, where the SIMD core computes a first set of stages and the one or more scalar cores compute the second set of stages. In one embodiment, a process for designing a heterogeneous multicore processor is disclosed which optimizes the ratio of scalar to SIMD cores based on execution time of the multi-stage compute operation in relation to processor die area consumed by a processor configuration having the ratio.

Heterogeneous multiprocessor including scalar and SIMD processors in a ratio defined by execution time and consumed die area

An apparatus and method are described for efficiently transferring data from a core of a central processing unit (CPU) to a graphics processing unit (GPU). For example, one embodiment of a method comprises: writing data to a buffer within the core of the CPU until a designated amount of data has been written; upon detecting that the designated amount of data has been written, responsively generating an eviction cycle, the eviction cycle causing the data to be transferred from the buffer to a cache accessible by both the core and the GPU; setting an indication to indicate to the GPU that data is available in the cache; and upon the GPU detecting the indication, providing the data to the GPU from the cache upon receipt of a read signal from the GPU.

Apparatus and method for memory-hierarchy aware producer-consumer instruction

In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for implementing efficient communication between caches in hierarchical caching design. For example, in one embodiment, such means may include an integrated circuit having a data bus; a lower level cache communicably interfaced with the data bus; a higher level cache communicably interfaced with the data bus; one or more data buffers and one or more dataless buffers. The data buffers in such an embodiment being communicably interfaced with the data bus, and each of the one or more data buffers having a buffer memory to buffer a full cache line, one or more control bits to indicate state of the respective data buffer, and an address associated with the full cache line. The dataless buffers in such an embodiment being incapable of storing a full cache line and having one or more control bits to indicate state of the respective dataless buffer and an address for an inter-cache transfer line associated with the respective dataless buffer. In such an embodiment, inter-cache transfer logic is to request the inter-cache transfer line from the higher level cache via the data bus and is to further write the inter-cache transfer line into the lower level cache from the data bus.

Methods and apparatus for efficient communication between caches in hierarchical caching design

In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for cutting senior store latency using store prefetching. For example, in one embodiment, such means may include an integrated circuit or an out of order processor means that processes out of order instructions and enforces in-order requirements for a cache. Such an integrated circuit or out of order processor means further includes means for receiving a store instruction; means for performing address generation and translation for the store instruction to calculate a physical address of the memory to be accessed by the store instruction; and means for executing a pre-fetch for a cache line based on the store instruction and the calculated physical address before the store instruction retires.

Method and apparatus for cutting senior store latency using store prefetching

A method for synchronizing a receiver to a stream of transmitted symbols that includes a known synchronization word. The method includes receiving a signal in which the symbols, including the synchronization word, are encoded by frequency shift keying. The signal is sampled and digitized to generate a sequence of input samples. For each of the input samples, a phase difference is determined relative to a preceding input sample in the sequence, thereby generating a sequence of differential samples corresponding respectively to the input samples. The differential samples are then matched to the synchronization word.

GFSK receiver

Growing community of inventors

Ceaseria, Israel

Ron Shalev