Nxp Usa, Inc.

Ron Michael Bar

Eran Glickman

Benny Michalovich

Dmitriy Shurin

Evgeni Ginzburg

Hezi Rahamim

Amir David Modan

Idan Ben Ami

Thomas Riesenberg

Omer Sharon

An interconnect offload component arranged to operate in an offloading mode, and a memory access component for enabling access to a memory element for functional data transmitted over a debug network of a signal processing device. In the offloading mode the interconnect offload component is arranged to receive functional data from an interconnect client component for communication to a destination component, and forward at least a part of the received functional data to a debug network for communication to the destination component via the debug network. The memory access component is arranged to receive a debug format message transmitted over the debug network, extract functional data from the received debug format message, said functional data originating from an interconnect client component for communication to a memory element, and perform a direct memory access to the memory element comprising the extracted functional data.

Method and apparatus for offloading functional data from an interconnect component

A controller for operably coupling a drive unit to a host unit in a serial advanced technology attachment (SATA) system is described. The controller comprises a hardware processor arranged to: receive a plurality of SATA data frames; identify a first primitive sequence in at least one of the plurality of SATA data frames that adversely affects a performance of the SATA system; and replace the identified first primitive sequence with a second primitive sequence in response thereto.

Controller, SATA system and method of operation therefor

A processing system includes a data processor, an input, an output, a memory, an operation parser, and a timer manager instance controller. The input receives create-timer-manager-instance (CTMI) commands identifying a number of timers supported by a timer manager instance. The output provides responses including a CTMI response associated with the CTMI command. The operation parser receives the CTMI command from the input. The timer manager instance controller receive a control input from the operation parser based upon the CTMI command, and in response, allocates a block of memory locations in the memory based on the number of timers and provides a CTMI response to the output to indicate that the CTMI response was executed by the timer manager instance controller.

System and method for partitioning and managing timers in a virtualized system

A key generator including a low-power key adjust circuit, and a high-power key adjust circuit. The low-power key adjust circuit including a storage location to store an original key, a shifter to shift the original key by a number of steps to shift to create a first key, and an output to provide the first key. The high-power key adjust circuit including an input coupled to the output of the low-power key adjust circuit to receive the first key, a scrambler to scramble the first key to create a scrambled key, and select circuitry to select either the first key or the scrambled key to output from the high-power key adjust circuit based on a bit in a configuration register.

Application specific low-power secure key

A processing system includes a general purpose instruction based data processor, an input configured to receive a command written by the data processor, a timer manager controller configured to receive the command and to execute the command, and a debug interrupt timer controller (DITC) configured to determine that the command is directed to the DITC and to store configuration information that associates the command with an element of the processing system that is a source of the command, where the configuration information is included in the command.

System and method for autonomous time-based debugging

A layered network () to provide offload of data in a communication processor (). The layered network () includes a first set (S) of network elements at a first layer (L) and a second set (S) of one or more network elements at a second layer (L). The network elements of the first set (S) are configured for processing incoming data and the network elements of the second set (S) of one or more network elements at the second layer (L) are configured to process intermediate data received from the first set (S) of network elements. The network elements of a particular subset (S) of the network elements of the first set (S) of network elements are connected to only a particular network element (E) of the second set (S) to transfer the incoming data processed by the network elements of the particular subset (S) to the particular network element (E) of the second set (S). The layered network () further includes a powering controller () configured to, during offload of the data, put a particular network element (E) of the second set (S) at the second layer (L) in an on state only if at least a particular network element (E) of the particular subset (S) of the network elements of the first set (S) at the first layer (L) is in an on state and at least one of the network elements of the first set (S) is in an off state. The powering controller () is configured to discriminate between chains of network elements formed by at least network elements of the first set (S) and network elements of the second set (S) and to have a chain in an on state if a first network element of the chain at a highest layer hierarchy is in an on state.

Selectively powered layered network and a method thereof

A data processing device comprises a protection key unit, a dummy key unit, and a control unit. The protection key unit provides a protection key. The dummy key unit provides a dummy key. The dummy key unit has a set of two or more allowed dummy key values associated with it and is configurable by a user or a host device to set the dummy key to any value selected from said set of allowed dummy key values. The control unit is connected to the dummy key unit and to the protection key unit and arranged to set the protection key to the value of the dummy key in response to a tamper detection signal (fatal_sec_vio) indicating a tamper event. The value of the dummy key may notably be different from zero. A method of protecting a data processing device against tampering is also described.

Data processing device and method for protecting a data processing device against tampering

A timer distribution module supports multiple timers and comprises: a command decoder arranged to determine expiration times of a plurality of timers; and a timer link list distribution adapter, LLDA, operably coupled to the command decoder. The LLDA is arranged to: receive a time reference from a master clock; receive timer data from the command decoder wherein the timer data comprises at least one timer expiration link list; construct a plurality of timer link lists based on at least one of: the timer expiration link list, at least one configurable timing barrier; dynamically split the link list timer data into a plurality of granularities based on the timer expiration link list; and output the dynamically split link list timer data.

Methods and apparatus for adaptive time keeping for multiple timers

An integrated circuit device comprises a data storage array controller for providing data storage array functionality for at least one data storage array. The data storage array controller comprises an address window controller arranged to receive at least one data storage device access command, and upon receipt of the at least one data storage device access command the address window controller is arranged to compare a target address of the at least one data storage device access command to an address window for a target storage device of the at least one data storage device access command, and if the target address is outside of the address window for the target storage device, block the at least one data storage device access command.

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Omer, Israel

Ron Michael Bar