Hewlett-Packard Development Company, L.p.

Hewlett-Packard Company

Other

Hewlett Packard Enterprise Development LP

Agilent Technologies, Inc.

Technion Research & Development Foundation Ltd

Ben-Gurion University of the Negev Research and Development Authority

Interdisciplinary Center Herzliya

Ron M Roth

Erik Ordentlich

Gadiel Seroussi

Josh N Hogan

Richard Stanley Williams

Philip John Kuekes

Gregory Stuart Snider

Ian F Blake

Pascal Vontobel

Peter G Webb

Gitit Ruckenstein

Warren J Robinett

Anat Bremler-Barr

David Hay

Giacomo Pedretti

Danny Hendler

Joseph Warren Robinett

Zohar Yakhini

Lei Zhao

Gregory S Smider

Gadlel Seroussl

J Warren Roblnett

Gadiel Seroissi

A device includes a first programmable computing block with an analog content addressable memory array, sense amplifiers, inverters, and a format converter circuit. The array includes analog content addressable memory cells arranged in rows and columns. The format converter circuit is configured to receive a Gray code from the inverters and convert it to a binary code. The device may also include additional programmable computing blocks. A system calculates decimal outputs of a predetermined function for a set of decimal inputs, encodes the outputs into Gray codes, generates mappings associating ranges of the decimal inputs with values for bit positions within the Gray codes, and programs the analog content addressable memory device based on the mappings to directly output the values for the bit positions.

Gray encoding for analog content addressable memory in general computing

A method for encoding bits to be stored within a crossbar memory architecture performed by a physical computing system includes designating, with the physical computing system, a subset of crosspoints within a crossbar matrix, the crossbar matrix comprising a number of disjointed intersecting wire segments, the subset corresponding to a predetermined path through the crossbar matrix; and encoding, with the physical computing system, a number of data bits to be placed along the predetermined path; in which the encoding causes bits pertaining to at least one of the wire segments to be subject to a constraint when the data bits are placed along the predetermined path.

Coding for crossbar architecture

A method is provided to manage access to a memory array. The method includes encoding a bit string with a rank metric encoder to generate an encoded binary array, modifying the encoded binary array so each row has at most half of the row with a bit value and each column has at most half of the column with the bit value, and storing the modified binary array into corresponding memory devices of the memory array.

Memory controller using crisscross error-correcting codes

A method of storing data into a memory array converts an input string into a first binary array with (m&#x2212;1) rows and (n&#x2212;1) columns. A second binary array with m rows and n columns in an encoded bit pattern is then generated from the first binary array. The second binary array in the encoded bit pattern has at most n/2 1's in each row and at most m/2 1's in each column, and the m-th row and an n-th column contain information for decoding other entries of the second binary array. The encoded bit pattern of the second binary array is then stored into corresponding memory devices of the memory array.

Method and system for encoding data for storage in a memory array

Examples of the present invention include an electronic-memory-system component. The electronic-memory-system component includes an array of data-storage elements and an encoder that receives input data, processes the input data as a two-dimensional array of bits by carrying out two passes, in one pass subjecting a portion of each row of the two-dimensional array of bits having more than a threshold weight to a first weight-reduction operation, and, in another pass, subjecting a portion of each considered column of the two-dimensional array of bits having more than a threshold weight to a second weight-reduction operation, one of the first and second weight-reduction operations employing an antipodal mapping and the other of the first and second weight-reduction operations employing bit inversion, generates a codeword corresponding to the input data, and stores the codeword in the array of data-storage elements.

Antipodal-mapping-based encoders and decoders

A multi-state memory system with encoding that minimizes half-select currents. The system includes an array of row and column conductors with a plurality of storage cells each capable of being placed into any of three or more physical states. An encoder is connected to receive data bits for storage and to apply activation signals to the row and column conductors to write information to the storage cells. The encoder is programmed to encode the data bits into entries in an array having one row corresponding with each row conductor and one column corresponding with each column conductor; select entries in the array according to half-select currents of the storage cells; apply a predetermined one-dimensional mapping that increases the value of at most one entry in the array to obtain a mapped array; and write entries of the mapped array into the storage cells.

Minimized half-select current in multi-state memories

A programmable crossbar array with inline fuses includes a layer of row lines and a layer of column lines with the row lines crossing over the column lines to form junctions and resistive memory elements sandwiched between row lines and a column lines at the junctions. Inline fuses are located in either the row lines, column lines or both. The inline fuses are interposed between the support circuitry and the resistive memory elements. A method for mitigating shorts in a crossbar array is also provided.

Inline fuses in programmable crossbar arrays

An approximate enumerative coding method () and apparatus () employ a cardinality-approximating (C-A) lower bound in mapping a message M to a 2-dimensional (2-D) codeword array that satisfies a 2-D constraint. The method () includes encoding the message M as a codeword array X using an encoder apparatus. The encoding determines entries in a codeword array X using the C-A lower bound. The C-A lower bound is a function of several terms, namely a memory term k, a cardinality of a set of sequences satisfying a horizontal constraint, a columnar extension probability of the 2-D constraint, and a non-negative constant that is a function of the columnar extension probability. The apparatus () includes an encoder processor (), memory () and a computer program () stored in the memory () and executed by the encoder processor ().

Approximate enumerative coding method and apparatus

A method for error detection includes storing in an associative memory multiple data entries, each data entry including a data item together with one or more check symbols computed with respect to the data item. A predetermined sequence of search keys is applied to the memory, thereby causing the memory to generate, in parallel, match results with respect to the data entries. The match results are processed in order to identify an error in at least one of the data entries.

Efficient detection of errors in associative memory

A data storage system including a memory array including a plurality of memory devices programmable in greater than two states. A memory control module may control operations of the memory array, and an encoder module may encode input data for storing to the memory array. The memory array may be an m&#xd7;n memory array, and the memory control module may control operations of storing data to and retrieving data from the memory array.

Memory array including multi-state memory devices

A data storage system including a memory array including a plurality of memory devices programmable in greater than two states. A read/write control module may overwrite data in the memory array without violating a constraint during the overwrite process. The memory array may be an m&#xd7;n memory array.

Overwriting a memory array

A method for encoding data to be placed into a weight constrained memory array includes designating a set of crosspoints within a crossbar memory array as indicator crosspoints and a set of crosspoints within the memory array as data crosspoints, the set of indicator crosspoints selected so that a net number of times that each data crosspoint has been flipped can be determined from a subset of the set of indicator crosspoints, placing an input stream of data into a matrix corresponding to crosspoints within the memory array, bits of the input stream being placed into matrix elements that correspond to data crosspoints of the memory array, setting each matrix element corresponding to indicator crosspoints to a value corresponding to a fixed resistive state, and flipping each bit corresponding to a conductor of the memory array until no conductors within the memory array violate a weight constraint.

Encoding data based on weight constraints

Method and system embodiments of the present invention are directed to encoding information in ways that are compatible with constraints associated with electrical-resistance-based memories and useful in other, similarly constrained applications, and to decoding the encoded information. One embodiment of the present invention encodes k information bits and writes the encoded k information bits to an electronic memory, the method comprising systematically encoding the k information bits to produce a vector codeword, with additional parity bits so that the codeword is resilient to bit-transition errors that may occur during storage of the codeword in, and retrieval of the codeword from, the electronic memory, ensuring that the codeword does not violate a weight constraint, and writing the codeword to the electronic memory.

Systems and methods for encoding information for storage in an electronic memory and for decoding encoded information retrieved from an electronic memory

Embodiments of the present invention include defect-tolerant demultiplexer crossbars that employ, or that can be modeled by demultiplexer crossbars that employ, threshold logic 'TL' elements. The threshold-logic elements provide for tolerance for signal variation on internal signals lines of a defect-tolerant demultiplexer crossbar, and thus tolerance for defects which produce internal signal variation.

Defect-tolerant demultiplexers based on threshold logic

Various embodiments of the present invention include methods for determining nanowire addressing schemes and include microscale/nanoscale electronic devices that incorporate the nanowire addressing schemes for reliably addressing nanowire-junctions within nanowire crossbars. The addressing schemes allow for change in the resistance state, or other physical or electronic state, of a selected nanowire-crossbar junction without changing the resistance state, or other physical or electronic state, of the remaining nanowire-crossbar junctions, and without destruction of either the selected nanowire-crossbar junction or the remaining, non-selected nanowire-crossbar junctions. Additional embodiments of the present invention include nanoscale memory arrays and other nanoscale electronic devices that incorporate the nanowire-addressing-scheme embodiments of the present invention. Certain of the embodiments of the present invention employ constant-weight codes, a well-known class of error-control-encoding codes, as addressed-nanowire selection voltages applied to microscale output signal lines of microscale/nanoscale encoder-demultiplexers that are selectively interconnected with a set of nanowires.

Growing community of inventors

Haifa, Israel

Ron M Roth