Samsung Electronics Co., Ltd.

Ron Golan

Amit Berman

Evgeny Blaichman

Sergey Gendel

Systems and methods of the present disclosure may be used to improve equalization module architectures for NAND cell read information. For example, embodiments of the present disclosure may provide for de-noising of NAND cell read information using a Multiple Shallow Threshold-Expert Machine Learning Models (MTM) equalizer. An MTM equalizer may include multiple shallow machine learning models, where each machine learning model is trained to specifically solve a classification task (e.g., a binary classification task) corresponding to a weak decision range between two possible read information values for a given NAND cell read operation. Accordingly, during inference, each read sample with a read value within a weak decision range is passed through a corresponding shallow machine learning model (e.g., a corresponding threshold expert) that is associated with (e.g., trained for) the particular weak decision range.

De-noising using multiple threshold-expert machine learning models

A method, apparatus, non-transitory computer readable medium, and system for using an error correction code in a memory device with a neural network are described. Embodiments of the method, apparatus, non-transitory computer readable medium, and system may receive a signal from a physical channel, wherein the signal is based on a modulated symbol representing information bits encoded using an error correction coding scheme, extract features from the signal using a feature extractor trained using probability data collected from the physical channel, and decode the information bits with a neural network decoder taking the extracted features as input.

Polar neural network decoder for memory devices

A memory system including a memory device and a memory controller including a processor. The memory controller is configured to read outputs from the memory cells in response to a read command from a host and to convert the read outputs to a first codeword. The processor performs a first error correcting code (ECC) operation on the first codeword. The processor is further configured to apply, for each selected memory cell among the memory cells, a corresponding one of the read outputs and at least one related feature as input features to a machine learning algorithm to generate a second codeword, and the memory controller is configured to perform a second ECC operation on the second codeword, when the first ECC operation fails.

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Shoham, Israel

Ron Golan