Intel Corporation

Ron Gabor

Joseph Nuzman

Tomer Stark

Raanan Sade

Lihu Rappoport

Igor Yanover

Ady Tal

Zeev Sperber

Theodros Yigzaw

David M Durham

Mohan J Kumar

Ashok Raj

Michael Mishaeli

Ido Ouziel

Hisham Shafi

Robert Valentine

Franck Sala

Naveen Kumar

Bryant E Bigbee

Shlomo Raikin

Shantanu R Gupta

Doron Shamia

Nadav Bonen

Oded Lempel

Chen Koren

Vjekoslav Svilan

Arkady Bramnik

Alex Gerber

David N Mackintosh

Jimmy Scott Raynor

Jose A Baiocchi Paredes

Lior Libis

Yoram Kulbak

Hong Jiang

Youfeng Wu

Doron Rajwan

Alon Naveh

Ohad Falik

David J Sager

Koichi Yamada

Stanislav Shwartsman

Sarathy Jayakumar

Sergiu D Ghetie

Tin-Fook Ngai

Ruchira Sasanka

Yuval Yosef

Suresh Srinivas

Randolph L Campbell

Neeraj S Upasani

Jayaram Bobba

Ho-Seop Kim

Ilhyun Kim

Omar M Shaikh

Gregory Pribush

James Varga

Leeor Peled

Yiannakis Sazeides

Howard Chen

Enrico Perla

Gady Yearim

Pankaj Raghuvanshi

Yulia Kurolap

Gilbert A Neiger

Vedvyas Shanbhogue

Siddhartha Chhabra

Efraim Rotem

Amit Gradstein

Hong Wang

Carlos V Rozas

Stephan Jourdan

Gad Shlomo Sheaffer

Rajat Agarwal

Nir Rosenzweig

Dan Baum

Xiang Chris Zou

Alaa R Alameldeen

Ehud Cohen

James Paul Held

Ofer Levy

Abhishek Basak

Zeev Offen

Julius Yuli Mandelblat

Larisa Novakovsky

Jeffrey J Cook

Deep K Buch

Avi Mendelson

Stephen J Robinson

Geeyarpuram N Santhanakrishnan

Jose Yallouz

Gavri Berger

Francis McKeen

Meir Tsadik

Bob Valentine

Uri C Weiser

Lev Makovsky

Kai Cong

Assaf Zaltsman

Fangfei Liu

Amir Leibovitz

Yoav Almog

Embodiments are directed to memory protection with hidden inline metadata. An embodiment of an apparatus includes processor cores; a computer memory for the storage of data; and cache memory communicatively coupled with one or more of the processor cores, wherein one or more processor cores of the plurality of processor cores are to implant hidden inline metadata in one or more cachelines for the cache memory, the hidden inline metadata being hidden at a linear address level.

Memory protection with hidden inline metadata

Techniques to allow use of metadata in unused bits of virtual addresses are described. A processor of an aspect includes a decode circuit to decode a memory access instruction. The instruction to indicate one or more memory address operands that are to have address generation information and metadata. An execution circuit coupled with the decode circuit to generate a 64-bit virtual address based on the one or more memory address operands. The 64-bit virtual address having a bit, an X-bit address field starting at a bitto store an address generated from the address generation information, and one or more metadata bits to store the metadata. The execution circuit also to perform a canonicality check on the 64-bit virtual address that does not fail due to non-canonical values of the metadata stored in the one or more metadata bits. Other processors, methods, systems, and instructions are disclosed.

64-bit virtual addresses having metadata bit(s) and canonicality check that does not fail due to non-canonical values of metadata bit(s)

Systems, methods, and apparatuses relating to linear address masking architecture are described. In one embodiment, a hardware processor includes an address generation unit to generate a linear address for a memory access request to a memory, at least one control register comprising a user mode masking bit and a supervisor mode masking bit, a register comprising a current privilege level indication, and a memory management unit to mask out a proper subset of bits inside an address space of the linear address for the memory access request based on the current privilege level indication and either of the user mode masking bit or the supervisor mode masking bit to produce a resultant linear address, and output the resultant linear address.

Apparatuses, methods, and systems for selective linear address masking based on processor privilege level and control register bits

An apparatus and method for tagged memory management. For example, one embodiment of a processor comprises: execution circuitry to execute instructions and process data, at least one instruction to generate a system memory access request having a first address pointer; and address translation circuitry to determine whether to translate the first address pointer with or without metadata processing, wherein if the first address pointer is to be translated with metadata processing, the address translation circuitry to: perform a lookup in a memory metadata table to identify a memory metadata value, determine a pointer metadata value associated with the first address pointer, and compare the memory metadata value with the pointer metadata value, the comparison to generate a validation of the memory access request or a fault condition, wherein if the comparison results in a validation of the memory access request, then accessing a set of one or more address translation tables to translate the first address pointer to a first physical address and to return the first physical address responsive to the memory access request.

Memory tagging apparatus and method

Embodiments of methods and apparatuses for restricted speculative execution are disclosed. In an embodiment, a processor includes configuration storage, an execution circuit, and a controller. The configuration storage is to store an indicator to enable a restricted speculative execution mode of operation of the processor, wherein the processor is to restrict speculative execution when operating in restricted speculative execution mode. The execution circuit is to perform speculative execution. The controller to restrict speculative execution by the execution circuit when the restricted speculative execution mode is enabled.

Restricted speculative execution mode to prevent observable side effects

An apparatus and method for tagged memory management, an embodiment including execution circuitry to generate a system memory access request having a first address pointer and address translation circuitry to determine whether to translate the first address pointer with metadata processing. The address translation circuitry is to access address translation tables to translate the first address pointer to a first physical address, perform a lookup in a memory metadata table to identify a memory metadata value associated with a physical address range including the first physical address, determine a pointer metadata value associated with the first address pointer, and compare the memory metadata value with the pointer metadata value; and when the comparison results in a validation of the memory access request, then return the first physical address.

Memory tagging metadata manipulation

Methods and apparatuses relating to memory corruption detection are described. In one embodiment, a hardware processor includes an execution unit to execute an instruction to request access to a block of a memory through a pointer to the block of the memory, and a memory management unit to allow access to the block of the memory when a memory corruption detection value in the pointer is validated with a memory corruption detection value in the memory for the block, wherein a position of the memory corruption detection value in the pointer is selectable between a first location and a second, different location.

Hardware apparatuses and methods for memory corruption detection

A processor of an aspect includes a decode unit to decode a read from memory instruction. The read from memory instruction is to indicate a source memory operand and a destination storage location. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the read from memory instruction, is to read data from the source memory operand, store an indication of defective data in an architecturally visible storage location, when the data is defective, and complete execution of the read from memory instruction without causing an exceptional condition, when the data is defective. Other processors, methods, systems, and instructions are disclosed.

Read from memory instructions, processors, methods, and systems, that do not take exception on defective data

One embodiment provides an apparatus. The apparatus includes a linear address space, metadata logic and enhanced address space layout randomization (ASLR) logic. The linear address space includes a metadata data structure. The metadata logic is to generate a metadata value. The enhanced ASLR logic is to combine the metadata value and a linear address into an address pointer and to store the metadata value to the metadata data structure at a location pointed to by a least a portion of the linear address. The address pointer corresponds to an apparent address in an enhanced address space. A size of the enhanced address space is greater than a size of the linear address space.

Enhanced address space layout randomization

Techniques and mechanisms for circuitry of a processor to automatically provide, and perform an operation based on, metadata indicating an uninitialized memory block. In an embodiment, processor circuitry detects a software instruction which specifies a first operation to be performed based on some data at a memory block. Metadata corresponding to said data comprises an identifier of whether the data is based on an uninitialized memory condition. Processing of the instruction, includes the processor circuitry automatically performing a second operation based on the identifier. The second operation is performed independent of any instruction of the application which specifies the second operation. In another embodiment, execution of the instruction (if any) is conditional upon an evaluation which is based on the state identifier, or the second operation is automatically performed based on an execution of the first instruction.

Device, system and method to detect an uninitialized memory read

In one embodiment, a method includes: in response to a sub-cacheline memory access request, receiving a data-line from a memory coupled to a processor; receiving tag information included in metadata associated with the data-line from the memory; determining, in a memory controller, whether a first tag identifier of the tag information matches a tag portion of an address of the memory line associated with the sub-cacheline memory access request, and in response to determining a match, storing a first portion of the data-line associated with the first tag identifier in a cache line of a cache of the processor, the first portion a sub-cacheline width. This method allows data lines stored in memory associated with multiple different tag metadata to be divided into multiple cachelines comprising the sub-cacheline data associated with a particular metadata address tag. Other embodiments are described and claimed.

System, apparatus and method for multi-cacheline small object memory tagging

Growing community of inventors

Hertzliya, Israel

Ron Gabor