Honeywell International Inc.

University of Arkansas

Nanowatt Design, LLC

Ron Foster

Richard Alan Davis

Richard A Kirkpatrick, Ii

Steve R Foote

Ajay Prabhakar Malshe

Jia Di

Scott Christopher Smith

Jerry Frenkil

Aaron Arthurs

Matthew W Kelley

A multi-rail module having mutually exclusive outputs. The module includes first and second-rail logic circuits, first and second-rail driver circuits, and a PMOS transistor sourcing Vto both the first and second driver circuits. The first-rail logic circuit is coupled to Vand ground and has a first logic input and a first logic output. The second-rail logic circuit is coupled to Vand ground and has a second logic input and a second logic output. The first-rail driver circuit is coupled to ground, receives the first logic output, and has a first-rail output Q. The second-rail driver circuit is coupled to ground, receives the second logic output, and has a second-rail output Q. The PMOS transistor has a gate driven by a SLEEP signal.

Single component sleep-convention logic (SCL) modules

A device having the capability for electrical, thermal, optical, and fluidic interconnections to various layers. Through-substrate vias in the interconnect device are filled to enable electrical and thermal connection or optionally hermetically sealed relative to other surfaces to enable fluidic or optical connection. Optionally, optical components may be placed within the via region in order to manipulate optical signals. Redistribution of electrical interconnection is accomplished on both top and bottom surfaces of the substrate of the interconnect chip.

Infinitely stackable interconnect device and method

Methods of and systems for balancing the capacitance of a common series capacitive circuit in a semiconductor-based sensor, such as a humidity sensor, are described. Relative humidity sensors can provide measurements via a series capacitive circuit including a humidity-sensitive dielectric separating a common top plate and first and second bottom plates associated with a first and second capacitor, Cxand Cx. For proper operation, the common top plate should be in capacitive balance. Capacitive balance can be achieved by creating voids within and/or along the common top plate of the sensor. A system for creating voids can include a precision cutting instrument, a measuring device for enabling the measurement of capacitance of at least one of the common series capacitive circuit, Cxand Cx, and power provided from a voltage source.

Methods and systems for capacitive balancing of relative humidity sensors having integrated signal conditioning

Methods of and systems providing high reliability relative humidity sensors having integrated signal conditioning are described, providing a series capacitive circuit including a humidity-sensitive dielectric, a common top plate and first and second bottom plates associated with a first and second capacitor, respectively. Changes in humidity affect the humidity-sensitive dielectric thereby causing changes in the capacitive value of said series capacitive circuit. The system includes a common top plate; a common humidity-sensitive dielectric formed under said common top plate; a first series capacitor Cx1 including a first bottom plate formed under said common humidity-sensitive dielectric opposite said common top plate; a second series capacitor Cx2 including a second bottom plate formed under said common humidity-sensitive dielectric opposite said common top plate; wherein said first series capacitor Cx1 and said second series capacitor Cx2 commonly share said dielectric and commonly share said common top plate and are arranged in a series capacitor circuit configuration within a semiconductor system. A sampling voltage source can provide a fixed voltage through said series capacitive circuit.

Relative humidity sensor with integrated signal conditioning

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Fayetteville, AR, United States of America

Ron Foster