IP Gem Group, LLC

Ron Cohen

Rino Micheloni

Amir Mosek

Alessia Marelli

Eran Kirzner

A nonvolatile memory system, a nonvolatile memory controller and a method for reducing latency of a memory controller are disclosed. The nonvolatile memory system includes a read circuit that performs background reads of an indicator page of each block to identify outlier blocks. A background reference positioning circuit performs background reads of representative pages of the outlier block at threshold voltage offsets to identify sets of updated threshold voltage offset values. Upon endurance events, retention timer events and read disturb events at a closed block background reads are performed of representative pages of the closed block at threshold voltage offsets to identify sets of updated threshold voltage offset values. When a usage characteristic meets one or more usage characteristic threshold, the read circuit performs subsequent host-requested reads of pages of blocks meeting the usage characteristic threshold using a threshold voltage shift read instruction and using the corresponding set of updated threshold voltage offset values.

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Tel Aviv, Israel

Ron Cohen