Verigy (singapore) Pte. Ltd.

Xilinx, Inc.

Advantest (singapore) Pte Ltd

Agilent Technologies, Inc.

Verigy Ipco

Silicon Test System, Inc.

Romi Mayder

John William Andberg

Paul Y Wu

Shuo Jiao

Christopher Paul Wyland

Randy L Bailey

Noriyuki Sugihara

Andrew Tse

Bowen Li

Atul V Ghia

Geoffrey Zhang

Paul T Sasaki

Mark A Alexander

Jian Tan

Ketan Sodha

Todd Sholl

Howard Johnson

Preeti Garg

Mike Augustin

Don Chiu

Nasser Ali Jafari

Edmundo Dela Puente

Pam Stellmacher

Apparatus and associated methods relate to predicting various transient output waveforms at a receiver's output after an initial neural network model is trained by a receiver's transient input waveform and a corresponding transient output waveform. In an illustrative example, the machine learning model may include an adaptive-ordered auto-regressive moving average external input based on neural networks (NNARMAX) model designed to mimic the performance of a continuous time linear equalization (CTLE) mode of the receiver. A Pearson Correlation Coefficient (PCC) score may be determined to select numbers of previous inputs and previous outputs to be used in the neural network model. In other examples, corresponding bathtub characterizations and eye diagrams may be extracted from the predicted transient output waveforms. Providing a machine learning model may, for example, advantageously predict various data patterns without knowing features or parameters of the receiver or related channels.

Machine learning based methodology for signal waveform, eye diagram, and bit error rate (BER) bathtub prediction

Apparatus and associated methods relate to providing a machine learning methodology that uses the machine learning's own failure experiences to optimize future solution search and provide self-guided information (e.g., the dependency and independency among various adaptation behavior) to predict a receiver's equalization adaptations. In an illustrative example, a method may include performing a first training on a first neural network model and determining whether all of the equalization parameters are tracked. If not all of the equalization parameters are tracked under the first training, then, a second training on a cascaded model may be performed. The cascaded model may include the first neural network model, and training data of the second training may include successful learning experiences and data of the first neural network model. The prediction accuracy of the trained model may be advantageously kept while having a low demand for training data.

Machine learning based methodology for adaptative equalization

In one embodiment, an integrated circuit (IC) includes a power distribution network having a first set of power distribution lines connected to a source voltage and a second set of power distribution lines connected to a ground voltage, and a first capacitor. A first variable resistive element is electrically coupled in series with the first capacitor between the first and second sets of power lines of the power distribution network. A control circuit is coupled to the variable resistive element and is configured and arranged to adjust a level of resistance of the first variable resistive element in response to an input signal. The adjustment of the level of resistance adjusts an equivalent series resistance of the power distribution network.

Dynamic configuration of equivalent series resistance

A method, and apparatus resulting from the method, for fabricating a circuit board suitable for mounting electronic components. The method includes drilling a plurality of through-holes in a plurality of dielectric sheets, forming a conductive film on at least one side of each of the plurality of dielectric sheets, and substantially filling each of the plurality of through holes with a conductive material. The conductive material is both electrically and thermally uninterrupted from a first face to a second face of each of the plurality of dielectric sheets. The plurality of dielectric sheets are then sequentially mounted, one atop another, to form the circuit board. The sequential mounting step is performed after the steps of drilling the plurality of through-holes, forming the conductive layer, and substantially filling the plurality of through-holes.

Methods for fabricating circuit boards

Integrated circuits are fabricated with mounted discrete capacitors. Bond pads and land pads are fabricated on a semiconductor wafer. Discrete capacitors are mounted on the semiconductor wafer with flexible adhesive. The flexible adhesive accommodates a difference in thermal expansion between the discrete capacitors and the semiconductor wafer. The land pads are electrically coupled to the electrodes of the discrete capacitors. The semiconductor wafer is separated into multiple semiconductor dice. The semiconductor dice are mounted in respective packages. The bond pads on each semiconductor die are electrically coupled to the interconnect terminals of the respective package.

Integrated circuit having a discrete capacitor mounted on a semiconductor die

In one embodiment, an integrated circuit (IC) is presented. The IC includes first and second sets of power distribution lines formed in the IC. The IC includes first and second capacitors formed in one or more layers of the IC. A first plurality of vias couple a first input of the first and second capacitors to the first set of power distribution lines, and a second plurality of vias couple a second input of the first and second capacitors to the second set of power distribution lines. The first capacitor and the first plurality of vias and the second plurality of vias coupled thereto having an equivalent series resistance greater than an equivalent series resistance of the second capacitor and the first plurality of vias and the second plurality of vias coupled thereto.

Power distribution network

A probe card assembly used to test electronic devices in an automated test equipment system. The probe card assembly includes a substrate having a plurality of through-holes contained therein and a plurality of electrical contact elements. Each of the plurality of electrical contact elements has characteristics of both a torsional beam and a cantilever beam design and is configured to scrub a test pad associated with the electronic device in two directions concurrently. The plurality of electrical contacts is configured to be magnetically aligned to the substrate. Each of the plurality of electrical contact elements is further configured to be removably adhered to the substrate thus allowing easy field replacement of individual electrical contact elements.

Element usable with the method, and a standalone probe card tester formable using the method

An electronic device for use with a probe head in automated test equipment includes first and second pluralities of semiconductor devices. The first plurality of semiconductor devices is arranged to form at least one driver arranged to couple to a device under test. The at least one driver is configured to transmit a signal to the at least one device under test. The second plurality of semiconductor devices is arranged to form at least one receiver arranged to couple to the device under test. The at least one receiver is configured to receive a signal from the at least one device under test. Each of the second plurality of semiconductor devices has a thickness less than about 300 &#x3bc;m exclusive of any electrical interconnects. The at least one receiver is adapted to mount directly to the probe head.

High impedance, high parallelism, high temperature memory test system architecture

Apparatus is for processing signals between a tester and devices under test. In one embodiment, the apparatus includes at least one multichip module. Each multichip module has a plurality of micro-electromechanical switches between a set of connectors to the tester and a set of connectors to devices under test. At least one driver is provided to operate each of the micro-electromechanical switches. A method of processing signals between a tester and devices under test is disclosed. In an embodiment, the method includes connecting the tester and the devices under test with at least one multichip module. Each of the at least one multichip module has a plurality of micro-electromechanical switches between a set of connectors to the tester and a set of connectors to the devices under test. The method includes operating each of the micro-electromechanical switches. Other embodiments are also disclosed.

Apparatus, systems and methods for processing signals between a tester and a plurality of devices under test at high temperatures and with single touchdown of a probe array

An electronic device for use with a probe head in automated test equipment. The device includes a plurality of semiconductor devices arranged to provide at least one driver/receiver pair where the driver portion of the driver/receiver pair is configured to transmit a signal to at least one device under test and the receiver portion of the driver/receiver pair is configured to receive a signal from the at least one device under test. Each of the plurality of semiconductor devices is fabricated using either a silicon-on-insulator (SOI) or metal-on-insulator (MOI) technology and has a thickness less than about 300 &#x3bc;m exclusive of any electrical interconnects. The at least one driver/receiver pair is adapted to mount directly to the probe head.

A method, and apparatus resulting from the method, for fabricating a circuit board suitable for mounting electronic components. The method includes drilling a plurality of through-holes in a plurality of dielectric sheets, forming a conductive film on at least one side of each of the plurality of dielectric sheets, and substantially filling each of the plurality of through holes with a conductive material. The conductive material is both electrically and thermally uninterrupted from a first face to a second face of each of the plurality of dielectric sheets. The plurality of dielectric sheets are then sequentially mounted, on atop another, to form the circuit board. The sequential mounting step is performed after the steps of drilling the plurality of through-holes, forming the conductive layer, and substantially filling the plurality of through-holes.

Solid high aspect ratio via hole used for burn-in boards, wafer sort probe cards, and package test load boards with electronic circuitry

A probe card with an air channel over the active components for cooling the active components on the probe card is provided.

Forced air cooling of components on a probecard

A water block heat dissipation on a probe card interface for cooling active components and other devices requiring heat dissipation on the probe card is presented.

Liquid cooled DUT card interface for wafer sort probing

In one embodiment, a method includes, providing a test program designed to control a circuit test system. The circuit test system has a plurality of test channels, each test channel of which is configured to be selectively coupled to a plurality of sub-channels under control of the test program. The method further includes 1) analyzing the test program to determine what combinations of channels, sub-channels and timing sets are required by the test program, and 2) in response to this analysis, creating a map of which timing sets, for which combinations of channels and sub-channels, should be pre-loaded into pin electronics that correspond to the test channels.

Method and apparatus for determining which timing sets to pre-load into the pin electronics of a circuit test system, and for pre-loading or storing said timing sets

A paddle board probe card for connecting a device under test with an ATE tester by means of ZIF connectors is presented. The paddle board probe card may include more than one printed circuit board mounted on a probe card in such a manner that the more than one printed circuit boards mate with ZIF connectors on an ATE testhead interface.

Growing community of inventors

San Jose, CA, United States of America

Romi Mayder