International Business Machines Corporation

Motorola Corporation

Freescale Semiconductor,inc.

Romesh Mangho Jessani

Soummya Mallick

Rajesh Bhikhubhai Patel

Belliappa Manavattira Kuttanna

Michael Putrino

David Cureton Baker

Antonio Torrini

Robert Greg McDonald

Albert John Loper

Sung-Ho Park

Robert Koelling

Mukesh Sharma

Muhammad Nural Afsar

Belliappa Manavattira Kuttana

Rajesh Bhikubhai Patel

Rajesh Bikhubhai Patel

An instruction set is executed from Read Only Memory (ROM). When a current instruction in the instruction set corresponds to a reserved patch memory block of ROM, a Random Access Memory (RAM) index and a ROM return address are loaded into a memory map, and a program counter is set to a first reserved ROM address. After jumping the program counter to the first reserved ROM address, the program counter is jumped to RAM based on the RAM index to execute a patch code, which includes at least one instruction to set the program counter to a second reserved ROM address. When the program counter equals the second reserved ROM address, the ROM return address is retrieved. Then the instruction set is executed from ROM based on the ROM return address.

Patching ROM code

A processor and method of processing a multiple-register instruction are described. The processor includes execution circuitry and a set of registers, which are each capable of storing a data word. A multiple-register instruction specifying a plurality of data words that are to be written to a corresponding plurality of registers within the set of registers is dispatched to the execution circuitry. In response to receipt of the multiple-register instruction, the execution circuitry executes the multiple-register instruction, such that at least two data words among the plurality of data words are written to at least two corresponding registers among the plurality of registers during a single cycle of the processor.

Method and system for processing a multiple-register instruction that

A processor and method for out-of-order execution of instructions are disclosed which fetch a first and a second instruction, wherein the first instruction precedes the second instruction in a program order. A determination is made whether execution of the second instruction is subject to execution of the first instruction. In response to a determination that execution of the second instruction is subject to execution of the first instruction, the second instruction is selectively executed prior to the first instruction in response to a parameter of at least one of the first and second instructions. In one embodiment, the parameter is an execution latency parameter of the first and second instructions.

Processor and method for out-of-order execution of instructions based

When the instruction dispatch unit detects two consecutive immediate instructions in the instruction queue directed to the same execution unit, it dispatches both during the same cycle, making use of both GPR ports for the two required GPR operands. Instruction path directing logic directs the first instruction to the execution decoder of the one execution unit during the first occurring cycle and latches the second instruction until a second occurring cycle. It also directs the first immediate operand of the first instruction to a first input of an execution block in the one execution unit during the first occurring cycle. An operand path directing logic directs the first GPR operand referred to by the first instruction to a second input of the execution block during the first occurring cycle and latches a second GPR operand referred to by the second instruction until the second occurring cycle. The instruction path directing logic directs the second instruction to the execution decoder during the second occurring cycle and directs the second immediate operand of the second instruction to the first input of the execution block during the second occurring cycle. The operand path directing logic directs the second GPR operand to the second input of the execution block during the second occurring cycle. In this manner, two instructions are dispatched in a single cycle from the instruction queue to one execution unit of the multiple execution unit parallel computer.

System and method for dispatching two instructions to the same execution

A method and system of implementing an early data dependency resolution mechanism for a high-performance data processing system that utilizes out-of-order instruction issue is disclosed. In accordance with the present disclosure, an instruction cache and a register-dependency cache are provided. The instruction cache has multiple cache lines, and each of these cache lines is capable of storing multiple instructions. The register-dependency cache contains an identical number of cache lines as in the instruction cache, and each of the cache lines within the register-dependency cache is capable of storing an identical number of register-dependency units as instructions in each of the cache lines within the instruction cache. In a single processor cycle, a group of register-dependency units are fetched from the register-dependency cache. All register-dependency units that have no forward data dependency within the group of register-dependency units are identified utilizing an Instruction Dispatch Unit. Each of the identified register-dependency units is then translated to its respective instruction utilizing a corresponding cache line within the instruction cache. All of the translated instructions are issued within a next processor cycle.

Method and system of implementing an early data dependency resolution

The present invention relates to a multiple stage execution unit for executing instructions in a microprocessor having a plurality of rename registers for storing execution results, an instruction cache for storing instructions, each instruction being associated with a rename register, a sequencer unit for providing an instruction to the execution unit, and a data cache for providing data to the execution unit. In one version, the execution unit includes a first stage which generates an intermediate result from the data according to an instruction; a means for providing a first portion of the intermediate result to an intermediate register; a means for providing a second portion of the intermediate result to a rename register associated with the instruction; a means for passing the first portion from the intermediate register to a second stage of the execution unit; a means for passing the second portion from the rename register to the second stage of the execution unit; wherein the second stage of the execution unit operates on the first and second portions according to the instruction.

Method and apparatus for dynamic allocation of registers for

A method and system for preventing information corruption in a cache memory due to a bus error which occurs during a cache linefill operation is disclosed. The cache memory includes multiple cache lines, and a tag is associated with each cache line. In accordance with the present disclosure, a tag associated with a cache line is validated before a linefill operation is performed on the cache line. In response to an occurrence of a bus error during the linefill operation, the tag associated with the cache line for which a linefill operation is performed, is invalidated such that the information within the cache line remains valid during a linefill operation unless a bus error occurs.

Method and system for preventing information corruption in a cache

A processor and method of executing instructions within a processor are disclosed, which permit both a branch instruction and a target instruction of the branch instruction to be executed in response to a single instruction fetch. In accordance with an illustrative embodiment, the processor, which has an associated memory, simultaneously fetches a plurality of instructions from the memory. Branch instructions among the plurality of instructions are then detected. In response to a detection of a branch instruction among the plurality of instructions, a determination is made whether a target instruction to be executed in response to execution of the branch instruction is one of the plurality of instructions. In response to a determination that the target instruction is one of the plurality of instructions, the processor executes the target instruction without making an additional instruction fetch.

Processor and method for executing a branch instruction and an

A data processing system having enhanced memory performance is provided. The data processing system comprises a processor that issues memory requests, a multilevel storage system including a first level cache, a second level cache, and a main memory connected to the processor in a memory hierarchy, and a memory controller. The memory controller retrieves a cache line from main memory, when a memory request for the cache line is received from the processor at the first level cache that causes a miss in both the first level cache and the second level cache. The memory controller loads the retrieved cache line in both the first level cache and the second level cache if the received memory request is a load request, and loads the retrieved cache line in only the first level cache and not the second level cache if the received memory request is a store request. The resultant reduction in reloads to the second level cache enhances memory performance by allowing immediate execution of subsequent memory requests to the second level cache and producing a higher hit rate as a result of the reduction in castouts from the second level cache.

Cache memory management system having reduced reloads to a second level

A microprocessor that dynamically shares cache capacity comprising a controller that determines if all ways for a congruence class of a requested instruction are valid in the instruction cache and if a replacement way for the congruence class of the requested instruction is valid in a data cache. A lookup for the instruction is performed in the cache tags for the instruction cache and the data cache. If a hit occurs in either cache, the instruction is retrieved. If a miss occurs for the instruction in both the instruction cache and the data cache, the controller loads the instruction into either the instruction cache, if the replacement way is valid in the data cache or at least one way for the congruence class of the requested instruction is not valid in the instruction cache, or the data cache, if the replacement way is not valid in the data cache and all ways for the congruence class of the requested instruction are valid in the instruction cache.

Growing community of inventors

Austin, TX, United States of America

Romesh Mangho Jessani