Intel Corporation

Romesh B Trivedi

Shankar Natarajan

Suresh Nagarajan

Zohar Bogin

Sriram Natarajan

Srinivasan T Rajappa

Anoop Mukker

Serafin E Garcia

Ramkarthik Ganesan

Arun Sitaram Athreya

Rajagopal Subramanian

Andrew M Volk

Sahar Khalili

Christine Watnik

Hou-Sheng Lin

Jennefer Asperheim

Scott Crippin

Buderya “Satish” Acharya

Power management circuitry in the solid state drive monitors activity on the plurality of media channels to coordinate an active period and an idle period using credits to manage a power budget for the solid state drive. The power management circuitry to coordinate active and idle periods across components in a workload pipeline in the solid state drive for a given performance target to obtain an optimal power and thermal profile.

Power and thermal management in a solid state drive

A solid state drive with a Logical To Physical (L2P) indirection table stored in a persistent memory is provided. The L2P indirection table has a plurality of entries, each entry to store a physical block address in the block addressable memory assigned to a logical block address. The solid state drive including solid state drive controller circuitry communicatively coupled to the persistent memory and the block addressable memory. The solid state drive controller circuitry including a volatile memory to store a logical to physical address indirection table cache and circuitry to monitor the logical to physical address indirection table cache and to write dirty logical to physical entries in the logical to physical address indirection table cache to the logical to physical address indirection table in the persistent memory.

Logical to physical address indirection table in a persistent memory in a solid state drive

Dirty Logical-to-Physical (L2P) entries in an L2P indirection table stored in a host volatile memory buffer are flushed to non-volatile memory in the solid state drive through the use of a write-back mode based on flush checkpoints. The use of write-back mode to flush dirty entries in the L2P indirection table to non-volatile memory in the solid state drive based on flush checkpoints results in an increase in the write bandwidth of the solid state drive.

Host managed buffer to store a logical-to physical address table for a solid state drive

A solid state drive (SSD) includes different segments of nonvolatile (NV) storage media with different access times. The NV media segment with faster access time operates as a cache for the segment with the slower access time. The SSD implements idle eviction from the cache segment to the other segment based on an idle condition of the SSD. The SSD can dynamically change application of the idle eviction based on a power management state indicated for the hardware platform. Thus, a change in power management state of the hardware platform associated with the SSD can cause the SSD to implement idle eviction differently.

Adaptive calibration of nonvolatile memory channel based on platform power management state

An apparatus is described that includes a solid state drive having non volatile buffer memory and non volatile primary storage memory. The non volatile buffer memory is to store less bits per cell than the non volatile primary storage memory. The solid state drive includes a controller to flush the buffer in response to a buffer flush command received from a host. The controller is to cause the solid state drive to service read/write requests that are newly received from the host in between flushes of smaller portions of the buffer's content that are performed to service the buffer flush command.

Mass storage device with host initiated buffer flushing

Systems, apparatuses and methods may provide for technology to determine a programmable eviction ratio associated with a storage device and convert a portion of a single-level cell region in the storage device into a multi-level cell region in accordance with the programmable eviction ratio. In one example, the amount of the portion converted into the multi-level cell region varies gradually as a function of percent capacity filled in the storage device.

Block management for dynamic single-level cell buffers in storage devices

According to one embodiment, computer system is disclosed. The computer system includes a central processing unit (CPU), a bus coupled to the CPU and a chipset coupled to the bus. The chipset includes compensation circuitry to compensate for process, voltage and temperature (PVT) effects attributed to a voltage change on the bus.

Method to detect a temperature change by a thermal monitor and compensating for process, voltage, temperature effects caused by the temperature change

A method and apparatus for a source synchronous address receiver for a system bus. In one embodiment, a flow-through between a system bus address input to a memory bus is controlled by two inputs: one is a source synchronous address strobe directing the receiver to latch the address and store data, while the other is a protocol signal, signaling the beginning of the address transfer. A flow-through circuit generates an enable signal in response to a digital address strobe signal and a digital address select signal to generate, prior to receipt of the address packet, an enable signal for a flow-through gate having the address packet and the enable signal as inputs. The flow-through gate provides the first component of the digital address packet (transaction address) to a chipset once the digital address packet appears on the address pin. Other embodiments are described and claimed.

Method and apparatus for a low latency source-synchronous address receiver for a host system bus in a memory controller

A method and apparatus for a source synchronous address receiver for a system bus is described. A flow-through between a system bus address input to a memory bus is controlled by two inputs: one is a source synchronous address strobe directing the receiver to latch the address and store data, while the other is a protocol signal, signaling the beginning of the address transfer. A flow-through circuit generates an enable signal in response to a digital address strobe signal and a digital address select signal to generate, prior to receipt of the address packet, an enable signal for a flow-through gate having the address packet and the enable signal as inputs. The flow-through gate provides the first component of the digital address packet (transaction address) to a chipset once the digital address packet appears on the address pin.

A glitch detection circuit is described for detecting a glitch on a strobe signal transmitted over a single strobe interface. The glitch detection circuit includes a first input terminal to receive a single strobe signal and a second input terminal to receive a protocol control signal. The glitch detection circuit uses a double edge detection circuit to detect two consecutive rising or falling edges on the strobe signal. The double edge detection circuit becomes initialized by an initializing circuit each time the logical state of the control signal changes from a first state to a second state. The glitch detection circuit is configured to output a glitch detection signal when two consecutive rising or falling edges are detected by the double edge detection circuit before being initialized by the initializing circuit.

Glitch detection circuit for outputting a signal indicative of a glitch on a strobe signal and initializing an edge detection circuit in response to a control signal

A method and circuit for programming an output buffer having a first output driver for producing a first signaling level with a first programmable strength and a second output driver for producing a second signaling level with a second programmable strength. The method includes coupling a test resistor between a source of the second signaling level and a mode terminal, sensing a first level at the mode terminal, and uncoupling the test resistor from the mode terminal. If the first level is between the second signaling level and a reference level, then programming the output buffer with reference to an unterminated transmission line coupled to the mode terminal. Otherwise, programming the output buffer with reference to an external resistor coupled between a source of the first signaling level and the mode terminal. The circuit includes a first counter coupled to the first comparator to produce a first value responsive to the mode flag, the mode terminal, and the reference level. A first latch, coupled to the first counter, provides the adjusted first value to the first output driver. A second latch, coupled to the second counter, provides the adjusted second value to the second output driver.

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Orangevale, CA, United States of America

Romesh B Trivedi