Nvidia Corporation

Intel Corporation

Roman Surgutchik

Brad W Simeral

David G Reed

Joshua Titus

Alon Naveh

Oded Lempel

Robert William Chapman

Stephen H Gunther

Robert J Greiner

Sean Jeffrey Treichler

Keng L Wong

Tezaswi Raja

Paul Gyugyi

Hung-Piao Ma

Brian Lawrence Smith

Kevin Dai

Anand Srinivasan

Robert Valentine

Murali Ramadoss

Gad Shlomo Sheaffer

Stephen Felix

Prashant Sethi

Ittai Anati

Tsvika Kurts

Dmitry Vyshetsky

Edward L Riegelsberger

Edward M Veeser

Hari Unni Krishnan

James P Reilley

Haim Lustig

Arie Chobotaro

Chinmay Apte

Raymond A Lui

Gad S Shaeffer

An on-chip electromagnetic (EM) pulse protection circuit detects EM pulse attacks, generates an alarm, and performs a defensive action to protect the integrated circuit. The EM pulse protection circuit can be used with various integrated circuits or manufactured chips in which, for example, there is a desire to keep information secure, maintain the security of the chip, secure boot processes, and/or protect private keys.

Protecting chips from electromagnetic pulse attacks using an antenna

A degradation detector for an integrated circuit (IC), a method of detecting aging in an IC and an IC incorporating the degradation detector or the method. In one embodiment, the degradation detector includes: (1) an offline ring oscillator (RO) coupled to a power gate and a clock gate, (2) a frozen RO coupled to a clock gate, (3) an online RO and (4) an analyzer coupled to the offline RO, the frozen RO and the online RO and operable to place the degradation detector in a normal state in which the offline RO is disconnected from both the drive voltage source and the clock source, the frozen RO is connected to the drive voltage source but disconnected from the clock source and the online RO is connected to both the drive voltage source and the clock source.

Degradation detector and method of detecting the aging of an integrated circuit

A data path controller, a computer device, an apparatus and a method are disclosed for integrating power management functions into a data path controller to manage power consumed by processors and peripheral devices. By embedding power management within the data path controller, the data path controller can advantageously modify its criteria in-situ so that it can adapt its power management actions in response to changes in processors and peripheral devices. In addition, the data path controller includes a power-managing interface that provides power-monitoring ports for monitoring and/or quantifying power consumption of various components. In one embodiment, the data path controller includes a power-monitoring interface for selectably monitoring power of a component. It also includes a controller for adjusting operational characteristics of the component for modifying the power consumed by the component to comply with a performance profile, which generally specifies permissible power consumption levels for the component.

Data path controller with integrated power management to manage power consumption of a computing device and its components

A speculative transfer mechanism transfers a source synchronous read request from a first clock domain to a second clock domain. The address portion having address information is transferred to the second clock domain in response to detecting a source synchronous address strobe latching signal. A pointer is generated in response to detecting the address strobe latching signal and passed into the second clock domain. In one embodiment, a pointer is retimed to be stable for a timing window for which a crossover of the address portion may be performed in the second clock domain. Request logic in the second clock domain generates a read command based on the address portion and the pointer.

Apparatus, system, and method for fast read request transfer through clock domains

A method and system for implementing a generalized system stutter are disclosed. Specifically, one embodiment of the present invention sets forth a method, which includes the steps of blocking a first request received from a first of a plurality of bus masters during a low power state of a computing device for as long as permissible by the timing requirements of the computing device, wherein the first request is capable of triggering the computing device to transition out of the low power state, and during an active state of the computing device, servicing the first request along with other pending requests from the rest of the plurality of bus masters before the computing device transitions back to the low power state.

Method and system for implementing generalized system stutter

Memory component temperature information is used to implement a method for ODT (on die termination) thermal load management. A respective temperature of a plurality of memory components are accessed, and based on this temperature, an ODT cycle is directed to a first of the memory components to avoid imposing a thermal load from the ODT cycle on a second of the memory components.

Method and system for memory thermal load sharing using memory on die termination

A system has a plurality of different clients. Each client generates a report signal indicative of a current latency tolerance associated with a performance state. A controller dynamically determines a power down level having a minimum power consumption capable of supporting the system latency of the configuration state of the clients.

Apparatus, method, and system for dynamically selecting power down level

A system is coupled to a network by a network interface. In a power savings mode the speed setting of the network interface is reduced to accommodate increased system latency.

Network interface speed adjustment to accommodate high system latency in power savings mode

A system, apparatus, and method are disclosed for increasing the physical memory size accessible to a processor, at least in part, by reclaiming physical address space typically associated with addresses of a restricted linear address space (i.e., addresses that are otherwise unusable by the processor as system memory). In one embodiment, an exemplary memory controller redirects a linear address associated with a range of addresses to access a reclaimed memory hole. The memory controller includes an address translator configured to determine an amount of restricted addresses and to establish a baseline address identified as a first number being a first integer power of 2. The range of addresses can be located at another address identified as a second number being a second integer power of 2. As such, the address translator translates the linear address into a translated address associated with the reclaimed memory hole based on the baseline address.

System, apparatus and method for reclaiming memory holes in memory composed of identically-sized memory devices

A system, apparatus, and method are disclosed for increasing the physical memory address space accessible to a processor, at least in part, by translating linear addresses associated with a memory hole into a subset of physical memory addresses that otherwise is inaccessible as system memory by a processor. In one embodiment, a memory controller reclaims memory holes in a system memory divided into ranges of linear addresses, where the system memory includes a number of arbitrarily-sized memory devices. The memory controller includes a memory configuration evaluator configured to determine a translated memory hole size for a memory hole, the memory hole including restricted linear addresses that translate into a subset of physical addresses. Also, memory configuration evaluator can be configured to form adjusted ranges to translate at least one linear address into a subset of physical addresses. As such, the system memory increases by at least the subset of physical addresses.

System, apparatus and method for reclaiming memory holes in memory composed of arbitrarily-sized memory devices

In one embodiment, there is provided a method comprising determining a target operating point for an electronic device, the target operating point including a target operating frequency and a target operating voltage; and dynamically changing a current operating point for the electronic device including a current operating frequency and a current operating voltage by non-contemporaneously changing the current operating frequency to the target operating frequency and a current operating voltage to the target operating voltage, wherein during the changing the electronic device is in an active state.

Method and apparatus to dynamically change an operating frequency and operating voltage of an electronic device

A method and system for memory temperature measurement. The method includes the step of monitoring a plurality of accesses to a memory component. A number of accesses occurring to the memory component over a time period is determined. A temperature of the memory component is determined based on the number of accesses occurring over the time period.

Method and system for memory temperature detection and thermal load management

An apparatus to determine if a temperature of an electronic device is equal to or exceeds a predetermined threshold. In response to detecting the temperature of the electronic device has at least reached the predetermined threshold, determining a target throttling point for a processor, the target throttling point including a target operating frequency and target operating voltage. Thereafter, dynamically changing a current operating point for the electronic device including a current operating frequency and a current operating voltage by non-contemporaneously changing the current operating frequency to the target operating frequency and the current operating voltage to the target operating voltage. During the changing of the current operating voltage the device is in an active state.

Growing community of inventors

Santa Clara, CA, United States of America

Roman Surgutchik