Micron Technology Incorporated

Round Rock Research, LLC

Roman Andreas Royer

Chikara Kondo

Chiaki Dono

Feng Lin

Methods, systems, and devices for reducing duty cycle degradation for a signal path are described. In some examples, a memory system may alternate a polarity of a signal line or signal path that includes a set of transistors during successive active periods of the memory system. In some cases, the memory device may include an inversion control component configured to operate the signal using either a first polarity or a second polarity. The inversion control component may receive an indication when the memory system enters an active period, and may accordingly alternate or the polarity of the signal path during successive active periods. In some examples, the signal path may be coupled with one or more output components which may uninvert signals from the signal path when the inversion control component has inverted the polarity of the signal path.

Reducing duty cycle degradation for a signal path

Embodiments of the disclosure are drawn to apparatuses, systems, and methods for direct access hybrid testing. A memory device, such as a high bandwidth memory (HBM) may include direct access terminals. During a testing procedure, test instructions may be provided to the memory through the direct access terminals. The test instructions include a data pointer which is associated with one of a plurality of test patterns pre-loaded in the memory and an address. The selected test pattern may be written to, and subsequently read from, the memory cells associated with the address. The read test pattern may be compared to the selected test pattern to generate result information. The test patterns may be loaded to the memory, and the result information may be read out from the memory, in an operational mode different than the operational mode in which the test instructions are provided.

Apparatuses and methods for direct access hybrid testing

Apparatuses including a test interface circuit that is configured to merge multiple independent traffic streams generated from individual algorithmic pattern generators (APGs) for communication with a memory device over a shared memory interface. The combination of multiple independent traffic streams, each with their own looping sequences and command timings, may generate a large set of random command sequences. The test interface circuit may include an arbiter circuit that merges a first independent traffic stream from a first APG and a second independent traffic stream from a second APG. Each of the first and second independent traffic streams are directed to different semi-independently-accessible portions of the memory device. The memory device may include a hybrid memory cube having independently accessible vaults or a high bandwidth memory device having independently accessible channels, in some examples. The test interface circuit may be included in a built-in self-test engine or in a standalone tester.

Multiple algorithmic pattern generator testing of a memory device

A memory device has multiple bi-directional data paths. One of the multiple bi-directional data paths is configured to transfer data at one speed. Another one of the multiple bi-directional data paths is configured to transfer data at another speed.

Memory device having data paths with multiple speeds

Embodiments of phase-generation circuitry and methods for generating a multiphase signal with duty-cycle correction are generally described herein. The phase-generation circuitry may include a plurality of controllable delay stages arranged in series and phase detector circuitry. Each delay stage may be configured to phase shift a differential signal based on a control signal. The phase detector circuitry may be configured to generate the control signal based on a first time difference and a second time difference. The first time difference may be a time difference between rising edges of a first component of the differential signal and a second component of a phase-shifted signal. The second time difference may be a time difference between falling edges of the first component of the differential signal and the second component of the phase-shifted signal. Other circuits, systems, and methods are described.

Phase-generation circuitry with duty-cycle correction and method for generating a multiphase signal

Embodiments of a multiphase generator with duty-cycle correction are generally described herein. In some embodiments, the multiphase generator comprises controllable delay stages arranged in series and dual-edge phase detector circuitry. The dual-edge phase detector circuitry may generate a control signal to adjust the delay provided by the delay stages based on corresponding rising edges and corresponding falling edges of same-state signals operated on by the delay stages. Other circuits, systems, and methods are described.

Multiphase generator with duty-cycle correction using dual-edge phase detection and method for generating a multiphase signal

A memory device has multiple bi-directional data paths. One of the multiple bi-directional data paths is configured to transfer data at one speed. Another one of the multiple bi-directional data paths is configured to transfer data at another speed. The memory device has different modes. Depending on a certain mode, the memory device uses different combinations of the multiple bi-directional data paths to transfer data either at a single speed or at multiple speeds. In some cases, the data represents data information to be stored in memory cells of the memory device. In other cases, the data represents control information and feedback information to be transferred to and from internal circuits, besides the memory cells, of the memory device.

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Boise, ID, United States of America

Roman Andreas Royer