International Business Machines Corporation

Shin-Etsu Chemical Co., Ltd.

Globalfoundries Inc.

Romain Lallement

Indira P Seshadri

Ruqiang Bao

Ekmini Anuja De Silva

Brent A Anderson

Junli Wang

Sivananda K Kanakasabapathy

Zhenxing Bi

Stuart A Sieg

Jing Guo

Tsutomu Ogihara

Hiroaki Niimi

Seiichiro Tachibana

Steven J Bentley

Nelson M Felix

Muthumanickam Sankarapandian

Karen Elizabeth Petrillo

Ardasheir Rahman

Liying Jiang

Hiroko Nagai

Gate metal is removed from a region containing transistors such as nanosheet transistors or vertical transport field-effect transistors using techniques that control the undercutting of gate metal in an adjoining region. A dielectric spacer layer is deposited on the transistors. A first etch causes the removal of gate metal over the boundary between the regions with limited undercutting of gate metal beneath the dielectric spacer layer. A subsequent etch removes the gate metal from the transistors in one region while the gate metal in the adjoining region is protected by a buffer layer. Gate dielectric material may also be removed over the boundary between regions.

Transistor structure with N/P boundary buffer

Methods for doping a semiconductor layer include forming a first mask on a first region of a semiconductor layer. A second region of the semiconductor layer, that is not covered by the first mask, is doped. A second mask is formed on the second region of the semiconductor layer. The first mask is etched away. The first region of the semiconductor layer is doped.

Self aligned block masks for implantation control

Transistor structure with n/p boundary buffer

A method for modeling planarization performance of a given material includes patterning a first photoresist layer over a first material deposited over a substrate. The method also includes etching portions of the first material exposed by the patterned first photoresist layer to create a patterned topography of the first material comprising two or more different design macros in two or more different regions. The method further includes coating the given material over the patterned topography of the first material, patterning a second photoresist layer over the given material, measuring the critical dimension of a metrology feature in each of the two or more different regions, and utilizing the measured critical dimensions of the metrology feature in the two or more different regions to generate a model of the planarization performance of the given material by relating the measured critical dimensions to focal planes of the given material.

Measuring and modeling material planarization performance

Embodiments of the invention include techniques for verifying planarization performance using electrical measures, the techniques include modeling, by a processor, a planarization layer for a topography of a device, and designing a chip including one or more structures. The techniques also include measuring electrical characteristics of the one or more structures, and comparing measured electrical characteristics of the one or more structures to target specifications for the one or more structures. Techniques include applying the planarization model to the one or more structures, and correlating the measured electrical characteristics to the planarization layer.

Verifying planarization performance using electrical measures

A semiconductor structure comprises a semiconductor substrate, an N-type stacked nanosheet channel structure formed on the semiconductor substrate, and a P-type stacked nanosheet channel structure formed adjacent to the N-type stacked nanosheet channel structure on the semiconductor substrate. Each of the adjacent N-type and P-type stacked nanosheet channel structures comprises a plurality of stacked channel regions with each such channel region being substantially surrounded by a gate dielectric layer and a gate work function metal layer, and with the gate work function metal layer being separated from the channel regions by the gate dielectric layer. The gate dielectric and gate work function metal layers of the adjacent N-type and P-type stacked nanosheet channel structures are substantially eliminated from a shared gate region between the adjacent N-type and P-type stacked nanosheet channel structures.

Low undercut N-P work function metal patterning in nanosheet replacement metal gate process

The present invention provides a resist multilayer film-attached substrate, including a substrate and a resist multilayer film formed on the substrate, in which the resist multilayer film has an organic resist underlayer film difficultly soluble in ammonia hydrogen peroxide water, an organic film soluble in ammonia hydrogen peroxide water, a silicon-containing resist middle layer film, and a resist upper layer film laminated on the substrate in the stated order. There can be provided a resist multilayer film-attached substrate that enables a silicon residue modified by dry etching to be easily removed in a wet manner with a removing liquid harmless to a semiconductor apparatus substrate and an organic resist underlayer film required in the patterning process, for example, an ammonia aqueous solution containing hydrogen peroxide called SC1, which is commonly used in the semiconductor manufacturing process.

Resist multilayer film-attached substrate and patterning process

A method of forming a merged source/drain region is disclosed that includes forming first and second VOCS structures above a semiconductor substrate, forming a recess in the substrate between the first and second VOCS structures and forming a P-type-doped semiconductor material in the recess. In this particular example, the method also includes removing a first substantially horizontally-oriented portion of the P-type-doped semiconductor material from within the recess while leaving a second substantially horizontally-oriented portion of the P-type-doped semiconductor material remaining in the recess and forming a substantially horizontally-oriented N-type-doped semiconductor material in the recess laterally adjacent the second substantially horizontally-oriented portion of the P-type-doped semiconductor material, wherein the substantially horizontally-oriented N-type-doped semiconductor material physically engages the second substantially horizontally-oriented portion of the P-type-doped semiconductor material along an interface within the merged source/drain region.

Methods of forming merged source/drain regions on integrated circuit products

Semiconductor devices and methods of forming the same include forming a wet-strippable hardmask over semiconductor fins. The wet-strippable hardmask is anisotropically etched away in a first device region. At least one semiconductor fin is doped in the first device region. The wet-strippable hardmask is isotropically etched away in a second device region. Semiconductor devices are formed from the fins in the first and second device regions.

Simplified block patterning with wet strippable hardmask for high-energy implantation

A method of forming a semiconductor structure includes forming first and second stacked nanosheet channel structures on a semiconductor substrate, with each nanosheet channel structure including a plurality of stacked channel regions interspersed with sacrificial regions. In a resulting semiconductor structure, an N-type stacked nanosheet channel structure is formed on the semiconductor substrate, and a P-type stacked nanosheet channel structure is formed adjacent to the N-type stacked nanosheet channel structure on the semiconductor substrate. Each of the adjacent N-type and P-type stacked nanosheet channel structures includes a plurality of stacked channel regions with each such channel region being substantially surrounded by a gate dielectric layer and a gate work function metal layer. The gate dielectric and gate work function metal layers of the adjacent N-type and P-type stacked nanosheet channel structures are substantially eliminated from a shared gate region between the adjacent N-type and P-type stacked nanosheet channel structures.

Growing community of inventors

Troy, NY, United States of America

Romain Lallement